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2,273 contributions in the last year
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Contribution activity
April 2025
Created 36 commits in 1 repository
Created a pull request in llvm/llvm-project that received 17 comments
[X86] combineConcatVectorOps - add concatenation handling for BITCAST nodes
These nodes are effectively free, so we should only concatenate if the inner nodes will concatenate together. This also exposed a regression in can…
Opened 18 other pull requests in 1 repository
llvm/llvm-project
17
merged
1
open
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[DAG] isSplatValue - only treat binop splats shared undef elements as undef
This contribution was made on Apr 14
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[X86] combineConcatVectorOps - require free concatenation of at least one operand of UNPCKL\H
This contribution was made on Apr 11
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[X86] lowerShuffleAsBitMask - generalize FP handling.
This contribution was made on Apr 11
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[X86] getConstVector - remove raw bits -> fp handling and leave it to getNode/FoldConstantArithmetic
This contribution was made on Apr 11
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[X86] combineGatherScatter - split non-constant (add v, (splat b)) indices patterns and add the splat into the (scalar) base address
This contribution was made on Apr 10
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[DAG] SDPatternMatch::ReassociatableOpc_match - pull out repeated pattern count expression. NFC.
This contribution was made on Apr 10
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[X86] getFauxShuffleMask - OR(BITCAST(SHUFFLE()),BITCAST(SHUFFLE())) patterns should return bitcasted source values
This contribution was made on Apr 9
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[X86] SimplifyDemandedVectorEltsForTargetNode - reduce the size of VPERMV v16f32/v16i32 nodes if the upper elements are not demanded
This contribution was made on Apr 8
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[X86] combineX86ShuffleChain - always prefer VPERMQ/PD for unary subvector shuffles on AVX2+ targets
This contribution was made on Apr 8
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[X86] combineX86ShufflesRecursively - iteratively peek through bitcasts to free subvector widening/narrowing sources.
This contribution was made on Apr 7
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[X86] SimplifyDemandedVectorEltsForTargetNode - reduce the size of VPERMV/VPERMV3 nodes if the upper elements are not demanded (REAPPLIED)
This contribution was made on Apr 3
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Revert "[X86] SimplifyDemandedVectorEltsForTargetNode - reduce the size of VPERMV/VPERMV3 nodes if the upper elements are not demanded"
This contribution was made on Apr 3
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[X86] Add growShuffleMask helper to grow the shuffle mask for a larger value type. NFC.
This contribution was made on Apr 3
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[X86] getFauxShuffleMask - move INSERT_SUBVECTOR(SRC0, EXTRACT_SUBVECTOR(SRC1)) matching behind common one use bitcast checks
This contribution was made on Apr 3
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[X86] getFauxShuffleMask - only handle VTRUNC nodes with matching src/dst sizes
This contribution was made on Apr 2
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[WIP][X86] combineX86ShufflesRecursively - attempt to combine shuffles with larger types from EXTRACT_SUBVECTOR nodes
This contribution was made on Apr 1
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[X86] SimplifyDemandedVectorEltsForTargetNode - reduce the size of VPERMV/VPERMV3 nodes if the upper elements are not demanded
This contribution was made on Apr 1
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[X86] combineX86ShuffleChain - prefer combining to X86ISD::SHUF128 if PERMQ operands are splittable
This contribution was made on Apr 1
Reviewed 42 pull requests in 1 repository
llvm/llvm-project
25 pull requests
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[X86][AVX] Match v4f64 blend from shuffle of scalar values.
This contribution was made on Apr 15
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[DAG] isSplatValue - only treat binop splats shared undef elements as undef
This contribution was made on Apr 14
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[AArch64] Add CostKind to getSpliceCost
This contribution was made on Apr 14
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release/20.x: [X86][AVX10] Remove VAES and VPCLMULQDQ feature from AVX10.1 (#135489)
This contribution was made on Apr 14
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[X86] Backport saturate-convert intrinsics renaming & YMM rounding intrinsics removal in AVX10.2
This contribution was made on Apr 14
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[CostModel] Make sure getCmpSelInstrCost is passed a CondTy
This contribution was made on Apr 14
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[CostModel] Remove some negative costs.
This contribution was made on Apr 14
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[CostModel] Plumb CostKind into getExtractWithExtendCost
This contribution was made on Apr 14
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[SLP]Synchronize cost of gather/buildvector nodes with codegen
This contribution was made on Apr 11
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release/20.x: [X86][SSE] Don't emit SSE2 load instructions in SSE1-only mode (#134547)
This contribution was made on Apr 11
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[SLP]Prefer segmented/deinterleaved loads to strided and fix codegen
This contribution was made on Apr 10
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[SLP][NFC]Extract preliminary checks from buildTree_rec, NFC
This contribution was made on Apr 10
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[X86] combineConcatVectorOps - add concatenation handling for BITCAST nodes
This contribution was made on Apr 10
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[DAG] SDPatternMatch - add matchers for reassociatable binops
This contribution was made on Apr 10
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[SLP]Support vectorization of previously vectorized scalars in split nodes
This contribution was made on Apr 10
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[SLP][NFC]Extract a check for a SplitVectorize node, NFC
This contribution was made on Apr 9
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[X86][DAGCombiner][SelectionDAG] - Fold Zext Build Vector to Bitcast of widen Build Vector
This contribution was made on Apr 9
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Reland "[SelectionDAG] Introducing a new ISD::POISON SDNode to represent the poison value in the IR."
This contribution was made on Apr 9
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[X86] SimplifyDemandedVectorEltsForTargetNode - reduce the size of VPERMV v16f32/v16i32 nodes if the upper elements are not demanded
This contribution was made on Apr 9
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[SLP][NFC]Extract a check for strided loads into separate function, NFC
This contribution was made on Apr 8
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[SLP][NFC]Extract TryToFindDuplicates lambda into a separate function, NFC
This contribution was made on Apr 8
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[X86][SSE] Don't emit SSE2 load instructions in SSE1-only mode
This contribution was made on Apr 8
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[X86] combineX86ShuffleChain - always prefer VPERMQ/PD for unary subvector shuffles on AVX2+ targets
This contribution was made on Apr 8
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[NFC] Use cast instead of dyn_cast for Src and Dst vec types in VecCombine folding
This contribution was made on Apr 8
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[IR] Deprecate PointerType::get/getUnqual pointee type overload
This contribution was made on Apr 7
- Some pull request reviews not shown.
Created an issue in llvm/llvm-project that received 3 comments
[X86] X86FixupVectorConstants generates SSE2 instructions on SSE1 targets
As detailed here: #134547
define void @store_v2f32_constant(ptr %v) { store <2 x float> <float 2.560000e+02, float 5.120000e+02>, ptr %v, align 4 r…
Opened 1 other issue in 1 repository
llvm/llvm-project
1
open
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[TTI] TargetTransformInfo - avoid default + inconsistent CostKinds
This contribution was made on Apr 14