[ARM] Treat strictfp vector rounding operations as legal by spavloff · Pull Request #180480 · llvm/llvm-project

spavloff · 2026-02-09T08:06:16Z

Previously, the strictfp variants of rounding operations (FLOOR, ROUND, etc) were handled in SelectionDAG via the default expansion, which splits vector operation into scalar ones. This results in less efficient code.

This change declares the strictfp counterparts of the vector rounding operations as legal and modifies existing rules in tablegen descriptions accordingly.

llvmbot · 2026-02-09T08:06:50Z

@llvm/pr-subscribers-backend-arm

Author: Serge Pavlov (spavloff)

Changes

Previously, the strictfp variants of rounding operations (FLOOR, ROUND, etc) were handled in SelectionDAG via the default expansion, which splits vector operation into scalar ones. This results in less efficient code.

This change declares the strictfp counterparts of the vector rounding operations as legal and modifies existing rules in tablegen descriptions accordingly.

Full diff: https://github.com/llvm/llvm-project/pull/180480.diff

5 Files Affected:

(modified) llvm/lib/Target/ARM/ARMISelLowering.cpp (+20)
(modified) llvm/lib/Target/ARM/ARMInstrMVE.td (+6-6)
(modified) llvm/lib/Target/ARM/ARMInstrNEON.td (+6-6)
(modified) llvm/test/CodeGen/ARM/fp-intrinsics-vector-v8.ll (+25-40)
(modified) llvm/test/CodeGen/Thumb2/mve-intrinsics/strict-intrinsics.ll (+1-16)

diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index b6a66d68fe5f2..86fbb1460f492 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -379,6 +379,13 @@ void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
       setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom);
       setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom);
 
+      setOperationAction(ISD::STRICT_FROUND, VT, Legal);
+      setOperationAction(ISD::STRICT_FROUNDEVEN, VT, Legal);
+      setOperationAction(ISD::STRICT_FRINT, VT, Legal);
+      setOperationAction(ISD::STRICT_FTRUNC, VT, Legal);
+      setOperationAction(ISD::STRICT_FFLOOR, VT, Legal);
+      setOperationAction(ISD::STRICT_FCEIL, VT, Legal);
+
       // No native support for these.
       setOperationAction(ISD::FDIV, VT, Expand);
       setOperationAction(ISD::FREM, VT, Expand);
@@ -1356,6 +1363,19 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM_,
       setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
       setOperationAction(ISD::FRINT, MVT::v2f32, Legal);
       setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
+
+      setOperationAction(ISD::STRICT_FFLOOR, MVT::v2f32, Legal);
+      setOperationAction(ISD::STRICT_FFLOOR, MVT::v4f32, Legal);
+      setOperationAction(ISD::STRICT_FROUND, MVT::v2f32, Legal);
+      setOperationAction(ISD::STRICT_FROUND, MVT::v4f32, Legal);
+      setOperationAction(ISD::STRICT_FROUNDEVEN, MVT::v2f32, Legal);
+      setOperationAction(ISD::STRICT_FROUNDEVEN, MVT::v4f32, Legal);
+      setOperationAction(ISD::STRICT_FCEIL, MVT::v2f32, Legal);
+      setOperationAction(ISD::STRICT_FCEIL, MVT::v4f32, Legal);
+      setOperationAction(ISD::STRICT_FTRUNC, MVT::v2f32, Legal);
+      setOperationAction(ISD::STRICT_FTRUNC, MVT::v4f32, Legal);
+      setOperationAction(ISD::STRICT_FRINT, MVT::v2f32, Legal);
+      setOperationAction(ISD::STRICT_FRINT, MVT::v4f32, Legal);
     }
 
     if (Subtarget->hasFullFP16()) {
diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td
index 1e9c141f13f83..8f874fed991f1 100644
--- a/llvm/lib/Target/ARM/ARMInstrMVE.td
+++ b/llvm/lib/Target/ARM/ARMInstrMVE.td
@@ -3605,12 +3605,12 @@ multiclass MVE_VRINT_m<MVEVectorVTInfo VTI, string suffix, bits<3> opcode,
 }
 
 multiclass MVE_VRINT_ops<MVEVectorVTInfo VTI> {
-  defm N : MVE_VRINT_m<VTI, "n", 0b000, froundeven>;
-  defm X : MVE_VRINT_m<VTI, "x", 0b001, frint>;
-  defm A : MVE_VRINT_m<VTI, "a", 0b010, fround>;
-  defm Z : MVE_VRINT_m<VTI, "z", 0b011, ftrunc>;
-  defm M : MVE_VRINT_m<VTI, "m", 0b101, ffloor>;
-  defm P : MVE_VRINT_m<VTI, "p", 0b111, fceil>;
+  defm N : MVE_VRINT_m<VTI, "n", 0b000, any_froundeven>;
+  defm X : MVE_VRINT_m<VTI, "x", 0b001, any_frint>;
+  defm A : MVE_VRINT_m<VTI, "a", 0b010, any_fround>;
+  defm Z : MVE_VRINT_m<VTI, "z", 0b011, any_ftrunc>;
+  defm M : MVE_VRINT_m<VTI, "m", 0b101, any_ffloor>;
+  defm P : MVE_VRINT_m<VTI, "p", 0b111, any_fceil>;
 }
 
 defm MVE_VRINTf16 : MVE_VRINT_ops<MVE_v8f16>;
diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td
index e2450490c83b8..f31938bb43d16 100644
--- a/llvm/lib/Target/ARM/ARMInstrNEON.td
+++ b/llvm/lib/Target/ARM/ARMInstrNEON.td
@@ -7349,12 +7349,12 @@ multiclass VRINT_FPI<string op, bits<3> op9_7, SDPatternOperator Int> {
   }
 }
 
-defm VRINTNN : VRINT_FPI<"n", 0b000, froundeven>;
-defm VRINTXN : VRINT_FPI<"x", 0b001, frint>;
-defm VRINTAN : VRINT_FPI<"a", 0b010, fround>;
-defm VRINTZN : VRINT_FPI<"z", 0b011, ftrunc>;
-defm VRINTMN : VRINT_FPI<"m", 0b101, ffloor>;
-defm VRINTPN : VRINT_FPI<"p", 0b111, fceil>;
+defm VRINTNN : VRINT_FPI<"n", 0b000, any_froundeven>;
+defm VRINTXN : VRINT_FPI<"x", 0b001, any_frint>;
+defm VRINTAN : VRINT_FPI<"a", 0b010, any_fround>;
+defm VRINTZN : VRINT_FPI<"z", 0b011, any_ftrunc>;
+defm VRINTMN : VRINT_FPI<"m", 0b101, any_ffloor>;
+defm VRINTPN : VRINT_FPI<"p", 0b111, any_fceil>;
 
 // Cryptography instructions
 let PostEncoderMethod = "NEONThumb2DataIPostEncoder",
diff --git a/llvm/test/CodeGen/ARM/fp-intrinsics-vector-v8.ll b/llvm/test/CodeGen/ARM/fp-intrinsics-vector-v8.ll
index 061834ab4eaf8..8cf3d40795f86 100644
--- a/llvm/test/CodeGen/ARM/fp-intrinsics-vector-v8.ll
+++ b/llvm/test/CodeGen/ARM/fp-intrinsics-vector-v8.ll
@@ -21,14 +21,11 @@ define <4 x float> @nearbyint_v4f32(<4 x float> %x) #0 {
 define <4 x float> @rint_v4f32(<4 x float> %x) #0 {
 ; CHECK-LABEL: rint_v4f32:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vmov d1, r2, r3
-; CHECK-NEXT:    vmov d0, r0, r1
-; CHECK-NEXT:    vrintx.f32 s7, s3
-; CHECK-NEXT:    vrintx.f32 s6, s2
-; CHECK-NEXT:    vrintx.f32 s5, s1
-; CHECK-NEXT:    vrintx.f32 s4, s0
-; CHECK-NEXT:    vmov r2, r3, d3
-; CHECK-NEXT:    vmov r0, r1, d2
+; CHECK-NEXT:    vmov d17, r2, r3
+; CHECK-NEXT:    vmov d16, r0, r1
+; CHECK-NEXT:    vrintx.f32 q8, q8
+; CHECK-NEXT:    vmov r0, r1, d16
+; CHECK-NEXT:    vmov r2, r3, d17
 ; CHECK-NEXT:    bx lr
   %val = call <4 x float> @llvm.experimental.constrained.rint.v4f32(<4 x float> %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
   ret <4 x float> %val
@@ -37,14 +34,11 @@ define <4 x float> @rint_v4f32(<4 x float> %x) #0 {
 define <4 x float> @round_v4f32(<4 x float> %x) #0 {
 ; CHECK-LABEL: round_v4f32:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vmov d1, r2, r3
-; CHECK-NEXT:    vmov d0, r0, r1
-; CHECK-NEXT:    vrinta.f32 s7, s3
-; CHECK-NEXT:    vrinta.f32 s6, s2
-; CHECK-NEXT:    vrinta.f32 s5, s1
-; CHECK-NEXT:    vrinta.f32 s4, s0
-; CHECK-NEXT:    vmov r2, r3, d3
-; CHECK-NEXT:    vmov r0, r1, d2
+; CHECK-NEXT:    vmov d17, r2, r3
+; CHECK-NEXT:    vmov d16, r0, r1
+; CHECK-NEXT:    vrinta.f32 q8, q8
+; CHECK-NEXT:    vmov r0, r1, d16
+; CHECK-NEXT:    vmov r2, r3, d17
 ; CHECK-NEXT:    bx lr
   %val = call <4 x float> @llvm.experimental.constrained.round.v4f32(<4 x float> %x, metadata !"fpexcept.strict") #0
   ret <4 x float> %val
@@ -53,14 +47,11 @@ define <4 x float> @round_v4f32(<4 x float> %x) #0 {
 define <4 x float> @roundeven_v4f32(<4 x float> %x) #0 {
 ; CHECK-LABEL: roundeven_v4f32:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vmov d1, r2, r3
-; CHECK-NEXT:    vmov d0, r0, r1
-; CHECK-NEXT:    vrintn.f32 s7, s3
-; CHECK-NEXT:    vrintn.f32 s6, s2
-; CHECK-NEXT:    vrintn.f32 s5, s1
-; CHECK-NEXT:    vrintn.f32 s4, s0
-; CHECK-NEXT:    vmov r2, r3, d3
-; CHECK-NEXT:    vmov r0, r1, d2
+; CHECK-NEXT:    vmov d17, r2, r3
+; CHECK-NEXT:    vmov d16, r0, r1
+; CHECK-NEXT:    vrintn.f32 q8, q8
+; CHECK-NEXT:    vmov r0, r1, d16
+; CHECK-NEXT:    vmov r2, r3, d17
 ; CHECK-NEXT:    bx lr
   %val = call <4 x float> @llvm.experimental.constrained.roundeven.v4f32(<4 x float> %x, metadata !"fpexcept.strict") #0
   ret <4 x float> %val
@@ -69,14 +60,11 @@ define <4 x float> @roundeven_v4f32(<4 x float> %x) #0 {
 define <4 x float> @floor_v4f32(<4 x float> %x) #0 {
 ; CHECK-LABEL: floor_v4f32:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vmov d1, r2, r3
-; CHECK-NEXT:    vmov d0, r0, r1
-; CHECK-NEXT:    vrintm.f32 s7, s3
-; CHECK-NEXT:    vrintm.f32 s6, s2
-; CHECK-NEXT:    vrintm.f32 s5, s1
-; CHECK-NEXT:    vrintm.f32 s4, s0
-; CHECK-NEXT:    vmov r2, r3, d3
-; CHECK-NEXT:    vmov r0, r1, d2
+; CHECK-NEXT:    vmov d17, r2, r3
+; CHECK-NEXT:    vmov d16, r0, r1
+; CHECK-NEXT:    vrintm.f32 q8, q8
+; CHECK-NEXT:    vmov r0, r1, d16
+; CHECK-NEXT:    vmov r2, r3, d17
 ; CHECK-NEXT:    bx lr
   %val = call <4 x float> @llvm.experimental.constrained.floor.v4f32(<4 x float> %x, metadata !"fpexcept.strict") #0
   ret <4 x float> %val
@@ -85,14 +73,11 @@ define <4 x float> @floor_v4f32(<4 x float> %x) #0 {
 define <4 x float> @ceil_v4f32(<4 x float> %x) #0 {
 ; CHECK-LABEL: ceil_v4f32:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vmov d1, r2, r3
-; CHECK-NEXT:    vmov d0, r0, r1
-; CHECK-NEXT:    vrintp.f32 s7, s3
-; CHECK-NEXT:    vrintp.f32 s6, s2
-; CHECK-NEXT:    vrintp.f32 s5, s1
-; CHECK-NEXT:    vrintp.f32 s4, s0
-; CHECK-NEXT:    vmov r2, r3, d3
-; CHECK-NEXT:    vmov r0, r1, d2
+; CHECK-NEXT:    vmov d17, r2, r3
+; CHECK-NEXT:    vmov d16, r0, r1
+; CHECK-NEXT:    vrintp.f32 q8, q8
+; CHECK-NEXT:    vmov r0, r1, d16
+; CHECK-NEXT:    vmov r2, r3, d17
 ; CHECK-NEXT:    bx lr
   %val = call <4 x float> @llvm.experimental.constrained.ceil.v4f32(<4 x float> %x, metadata !"fpexcept.strict") #0
   ret <4 x float> %val
diff --git a/llvm/test/CodeGen/Thumb2/mve-intrinsics/strict-intrinsics.ll b/llvm/test/CodeGen/Thumb2/mve-intrinsics/strict-intrinsics.ll
index 18a3fbc26219a..8dd02491d7040 100644
--- a/llvm/test/CodeGen/Thumb2/mve-intrinsics/strict-intrinsics.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-intrinsics/strict-intrinsics.ll
@@ -343,22 +343,7 @@ entry:
 define arm_aapcs_vfpcc <8 x half> @test_roundeven_f16(<8 x half> %a) #0 {
 ; CHECK-LABEL: test_roundeven_f16:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vmovx.f16 s4, s0
-; CHECK-NEXT:    vrintn.f16 s0, s0
-; CHECK-NEXT:    vrintn.f16 s4, s4
-; CHECK-NEXT:    vins.f16 s0, s4
-; CHECK-NEXT:    vmovx.f16 s4, s1
-; CHECK-NEXT:    vrintn.f16 s4, s4
-; CHECK-NEXT:    vrintn.f16 s1, s1
-; CHECK-NEXT:    vins.f16 s1, s4
-; CHECK-NEXT:    vmovx.f16 s4, s2
-; CHECK-NEXT:    vrintn.f16 s4, s4
-; CHECK-NEXT:    vrintn.f16 s2, s2
-; CHECK-NEXT:    vins.f16 s2, s4
-; CHECK-NEXT:    vmovx.f16 s4, s3
-; CHECK-NEXT:    vrintn.f16 s4, s4
-; CHECK-NEXT:    vrintn.f16 s3, s3
-; CHECK-NEXT:    vins.f16 s3, s4
+; CHECK-NEXT:    vrintn.f16 q0, q0
 ; CHECK-NEXT:    bx lr
 entry:
   %0 = tail call <8 x half> @llvm.experimental.constrained.roundeven.v8f16(<8 x half> %a, metadata !"fpexcept.strict")

arsenm · 2026-02-09T08:36:16Z

      setOperationAction(ISD::FRINT, MVT::v2f32, Legal);
      setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
+
+      setOperationAction(ISD::STRICT_FFLOOR, MVT::v2f32, Legal);


These should be paired with the non-strict op, like setOperationAction({FFLOOR, STRICT_FFLOOR}, VT, Legal)

arsenm · 2026-02-09T13:56:27Z

@@ -1,5 +1,5 @@
 BasedOnStyle: LLVM
-LineEnding: LF
+#LineEnding: LF


davemgreen · 2026-02-09T16:38:58Z

I see, these are probably OK if they don't raise inexact on flushes. Can you improve the MVE tests a little? Thanks.

davemgreen · 2026-02-09T16:40:28Z

@Varnike FYI if you have any other comments.

davemgreen

Please rebase now that the tests are in.

Previously, the strictfp variants of rounding operations (FLOOR, ROUND, etc) were handled in SelectionDAG via the default expansion, which splits vector operation into scalar ones. This results in less efficient code. This change declares the strictfp counterparts of the vector rounding operations as legal and modifies existing rules in tablegen descriptions accordingly.

davemgreen

LGTM, thanks

spavloff · 2026-02-20T04:01:10Z

Thanks!

Previously the strictfp rounding nodes were lowered using unrolling to scalar operations, which has negative impact on performance. Partially this issue was fixed in #180480, this change continues that work and implements optimized lowering for v4f16 and v8f16.

…lt mode (#183700) Previously the strictfp rounding nodes were lowered using unrolling to scalar operations, which has negative impact on performance. Partially this issue was fixed in #180480, this change continues that work and implements optimized lowering for v4f16 and v8f16.

…lt mode (llvm#183700) Previously the strictfp rounding nodes were lowered using unrolling to scalar operations, which has negative impact on performance. Partially this issue was fixed in llvm#180480, this change continues that work and implements optimized lowering for v4f16 and v8f16.

spavloff requested review from arsenm, davemgreen, john-brawn-arm and s-barannikov February 9, 2026 08:06

llvmbot added the backend:ARM label Feb 9, 2026

arsenm reviewed Feb 9, 2026

View reviewed changes

spavloff force-pushed the users/spavloff/arm.round branch from 0e4f54e to 378532d Compare February 10, 2026 16:30

Base automatically changed from users/spavloff/arm.test to main February 13, 2026 06:20

davemgreen reviewed Feb 16, 2026

View reviewed changes

spavloff added 4 commits February 16, 2026 18:21

Address review comments

9d04717

Remove stray change

45575a8

Update because dependency is changed

44ea2d1

spavloff force-pushed the users/spavloff/arm.round branch from 378532d to 44ea2d1 Compare February 16, 2026 12:54

davemgreen approved these changes Feb 19, 2026

View reviewed changes

Merge branch 'main' into users/spavloff/arm.round

d69eded

spavloff merged commit 19ebb0a into main Feb 20, 2026
10 checks passed

spavloff deleted the users/spavloff/arm.round branch February 20, 2026 05:37

spavloff mentioned this pull request Feb 27, 2026

[ARM] Lower strictfp vector fp16 rounding operations similar to default mode #183700

Merged

This was referenced Apr 15, 2026

[X86] regenerate fcopysign test checks (#183710) ampandey-1995/llvm-project#4

Closed

[X86] regenerate fcopysign test checks (#183710) ampandey-1995/llvm-project#5

Closed

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[ARM] Treat strictfp vector rounding operations as legal - #180480

[ARM] Treat strictfp vector rounding operations as legal#180480
spavloff merged 5 commits into
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