Skip to content

[ARM] Treat strictfp vector rounding operations as legal #180480

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
spavloff merged 5 commits into from
Feb 20, 2026
Merged

[ARM] Treat strictfp vector rounding operations as legal #180480

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
5 commits
Select commit Hold shift + click to select a range
18ae656
[ARM] Treat strictfp vector rounding operations as legal
spavloff Feb 5, 2026
9d04717
Address review comments
spavloff Feb 9, 2026
45575a8
Remove stray change
spavloff Feb 9, 2026
44ea2d1
Update because dependency is changed
spavloff Feb 10, 2026
d69eded
Merge branch 'main' into users/spavloff/arm.round
spavloff Feb 20, 2026
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
31 changes: 13 additions & 18 deletions llvm/lib/Target/ARM/ARMISelLowering.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -369,12 +369,12 @@ void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
if (HasMVEFP) {
setOperationAction(ISD::FMINNUM, VT, Legal);
setOperationAction(ISD::FMAXNUM, VT, Legal);
setOperationAction(ISD::FROUND, VT, Legal);
setOperationAction(ISD::FROUNDEVEN, VT, Legal);
setOperationAction(ISD::FRINT, VT, Legal);
setOperationAction(ISD::FTRUNC, VT, Legal);
setOperationAction(ISD::FFLOOR, VT, Legal);
setOperationAction(ISD::FCEIL, VT, Legal);
for (auto Op : {ISD::FROUND, ISD::STRICT_FROUND, ISD::FROUNDEVEN,
ISD::STRICT_FROUNDEVEN, ISD::FTRUNC, ISD::STRICT_FTRUNC,
ISD::FRINT, ISD::STRICT_FRINT, ISD::FFLOOR,
ISD::STRICT_FFLOOR, ISD::FCEIL, ISD::STRICT_FCEIL}) {
setOperationAction(Op, VT, Legal);
}
setOperationAction(ISD::VECREDUCE_FADD, VT, Custom);
setOperationAction(ISD::VECREDUCE_FMUL, VT, Custom);
setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom);
Expand Down Expand Up @@ -1350,18 +1350,13 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM_,
setOperationAction(ISD::FMAXIMUM, MVT::v4f32, Legal);

if (Subtarget->hasV8Ops()) {
setOperationAction(ISD::FFLOOR, MVT::v2f32, Legal);
setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
setOperationAction(ISD::FROUND, MVT::v2f32, Legal);
setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
setOperationAction(ISD::FROUNDEVEN, MVT::v2f32, Legal);
setOperationAction(ISD::FROUNDEVEN, MVT::v4f32, Legal);
setOperationAction(ISD::FCEIL, MVT::v2f32, Legal);
setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
setOperationAction(ISD::FTRUNC, MVT::v2f32, Legal);
setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
setOperationAction(ISD::FRINT, MVT::v2f32, Legal);
setOperationAction(ISD::FRINT, MVT::v4f32, Legal);
for (auto Op : {ISD::FROUND, ISD::STRICT_FROUND, ISD::FROUNDEVEN,
ISD::STRICT_FROUNDEVEN, ISD::FTRUNC, ISD::STRICT_FTRUNC,
ISD::FRINT, ISD::STRICT_FRINT, ISD::FFLOOR,
ISD::STRICT_FFLOOR, ISD::FCEIL, ISD::STRICT_FCEIL}) {
setOperationAction(Op, MVT::v2f32, Legal);
setOperationAction(Op, MVT::v4f32, Legal);
}
}

if (Subtarget->hasFullFP16()) {
Expand Down
12 changes: 6 additions & 6 deletions llvm/lib/Target/ARM/ARMInstrMVE.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3605,12 +3605,12 @@ multiclass MVE_VRINT_m<MVEVectorVTInfo VTI, string suffix, bits<3> opcode,
}

multiclass MVE_VRINT_ops<MVEVectorVTInfo VTI> {
defm N : MVE_VRINT_m<VTI, "n", 0b000, froundeven>;
defm X : MVE_VRINT_m<VTI, "x", 0b001, frint>;
defm A : MVE_VRINT_m<VTI, "a", 0b010, fround>;
defm Z : MVE_VRINT_m<VTI, "z", 0b011, ftrunc>;
defm M : MVE_VRINT_m<VTI, "m", 0b101, ffloor>;
defm P : MVE_VRINT_m<VTI, "p", 0b111, fceil>;
defm N : MVE_VRINT_m<VTI, "n", 0b000, any_froundeven>;
defm X : MVE_VRINT_m<VTI, "x", 0b001, any_frint>;
defm A : MVE_VRINT_m<VTI, "a", 0b010, any_fround>;
defm Z : MVE_VRINT_m<VTI, "z", 0b011, any_ftrunc>;
defm M : MVE_VRINT_m<VTI, "m", 0b101, any_ffloor>;
defm P : MVE_VRINT_m<VTI, "p", 0b111, any_fceil>;
}

defm MVE_VRINTf16 : MVE_VRINT_ops<MVE_v8f16>;
Expand Down
12 changes: 6 additions & 6 deletions llvm/lib/Target/ARM/ARMInstrNEON.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -7349,12 +7349,12 @@ multiclass VRINT_FPI<string op, bits<3> op9_7, SDPatternOperator Int> {
}
}

defm VRINTNN : VRINT_FPI<"n", 0b000, froundeven>;
defm VRINTXN : VRINT_FPI<"x", 0b001, frint>;
defm VRINTAN : VRINT_FPI<"a", 0b010, fround>;
defm VRINTZN : VRINT_FPI<"z", 0b011, ftrunc>;
defm VRINTMN : VRINT_FPI<"m", 0b101, ffloor>;
defm VRINTPN : VRINT_FPI<"p", 0b111, fceil>;
defm VRINTNN : VRINT_FPI<"n", 0b000, any_froundeven>;
defm VRINTXN : VRINT_FPI<"x", 0b001, any_frint>;
defm VRINTAN : VRINT_FPI<"a", 0b010, any_fround>;
defm VRINTZN : VRINT_FPI<"z", 0b011, any_ftrunc>;
defm VRINTMN : VRINT_FPI<"m", 0b101, any_ffloor>;
defm VRINTPN : VRINT_FPI<"p", 0b111, any_fceil>;

// Cryptography instructions
let PostEncoderMethod = "NEONThumb2DataIPostEncoder",
Expand Down
30 changes: 5 additions & 25 deletions llvm/test/CodeGen/ARM/fp-intrinsics-vector-v8.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -17,11 +17,7 @@ define <4 x float> @nearbyint_v4f32(<4 x float> %x) #0 {
define <4 x float> @rint_v4f32(<4 x float> %x) #0 {
; CHECK-LABEL: rint_v4f32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vrintx.f32 s7, s3
; CHECK-NEXT: vrintx.f32 s6, s2
; CHECK-NEXT: vrintx.f32 s5, s1
; CHECK-NEXT: vrintx.f32 s4, s0
; CHECK-NEXT: vorr q0, q1, q1
; CHECK-NEXT: vrintx.f32 q0, q0
; CHECK-NEXT: bx lr
%val = call <4 x float> @llvm.experimental.constrained.rint.v4f32(<4 x float> %x, metadata !"round.dynamic", metadata !"fpexcept.strict")
ret <4 x float> %val
Expand All @@ -30,11 +26,7 @@ define <4 x float> @rint_v4f32(<4 x float> %x) #0 {
define <4 x float> @round_v4f32(<4 x float> %x) #0 {
; CHECK-LABEL: round_v4f32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vrinta.f32 s7, s3
; CHECK-NEXT: vrinta.f32 s6, s2
; CHECK-NEXT: vrinta.f32 s5, s1
; CHECK-NEXT: vrinta.f32 s4, s0
; CHECK-NEXT: vorr q0, q1, q1
; CHECK-NEXT: vrinta.f32 q0, q0
; CHECK-NEXT: bx lr
%val = call <4 x float> @llvm.experimental.constrained.round.v4f32(<4 x float> %x, metadata !"fpexcept.strict")
ret <4 x float> %val
Expand All @@ -43,11 +35,7 @@ define <4 x float> @round_v4f32(<4 x float> %x) #0 {
define <4 x float> @roundeven_v4f32(<4 x float> %x) #0 {
; CHECK-LABEL: roundeven_v4f32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vrintn.f32 s7, s3
; CHECK-NEXT: vrintn.f32 s6, s2
; CHECK-NEXT: vrintn.f32 s5, s1
; CHECK-NEXT: vrintn.f32 s4, s0
; CHECK-NEXT: vorr q0, q1, q1
; CHECK-NEXT: vrintn.f32 q0, q0
; CHECK-NEXT: bx lr
%val = call <4 x float> @llvm.experimental.constrained.roundeven.v4f32(<4 x float> %x, metadata !"fpexcept.strict")
ret <4 x float> %val
Expand All @@ -56,11 +44,7 @@ define <4 x float> @roundeven_v4f32(<4 x float> %x) #0 {
define <4 x float> @floor_v4f32(<4 x float> %x) #0 {
; CHECK-LABEL: floor_v4f32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vrintm.f32 s7, s3
; CHECK-NEXT: vrintm.f32 s6, s2
; CHECK-NEXT: vrintm.f32 s5, s1
; CHECK-NEXT: vrintm.f32 s4, s0
; CHECK-NEXT: vorr q0, q1, q1
; CHECK-NEXT: vrintm.f32 q0, q0
; CHECK-NEXT: bx lr
%val = call <4 x float> @llvm.experimental.constrained.floor.v4f32(<4 x float> %x, metadata !"fpexcept.strict")
ret <4 x float> %val
Expand All @@ -69,11 +53,7 @@ define <4 x float> @floor_v4f32(<4 x float> %x) #0 {
define <4 x float> @ceil_v4f32(<4 x float> %x) #0 {
; CHECK-LABEL: ceil_v4f32:
; CHECK: @ %bb.0:
; CHECK-NEXT: vrintp.f32 s7, s3
; CHECK-NEXT: vrintp.f32 s6, s2
; CHECK-NEXT: vrintp.f32 s5, s1
; CHECK-NEXT: vrintp.f32 s4, s0
; CHECK-NEXT: vorr q0, q1, q1
; CHECK-NEXT: vrintp.f32 q0, q0
; CHECK-NEXT: bx lr
%val = call <4 x float> @llvm.experimental.constrained.ceil.v4f32(<4 x float> %x, metadata !"fpexcept.strict")
ret <4 x float> %val
Expand Down
102 changes: 6 additions & 96 deletions llvm/test/CodeGen/Thumb2/mve-strict-round.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -4,22 +4,7 @@
define arm_aapcs_vfpcc <8 x half> @test_rint_f16(<8 x half> %a) #0 {
; CHECK-LABEL: test_rint_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovx.f16 s4, s0
; CHECK-NEXT: vrintx.f16 s0, s0
; CHECK-NEXT: vrintx.f16 s4, s4
; CHECK-NEXT: vins.f16 s0, s4
; CHECK-NEXT: vmovx.f16 s4, s1
; CHECK-NEXT: vrintx.f16 s4, s4
; CHECK-NEXT: vrintx.f16 s1, s1
; CHECK-NEXT: vins.f16 s1, s4
; CHECK-NEXT: vmovx.f16 s4, s2
; CHECK-NEXT: vrintx.f16 s4, s4
; CHECK-NEXT: vrintx.f16 s2, s2
; CHECK-NEXT: vins.f16 s2, s4
; CHECK-NEXT: vmovx.f16 s4, s3
; CHECK-NEXT: vrintx.f16 s4, s4
; CHECK-NEXT: vrintx.f16 s3, s3
; CHECK-NEXT: vins.f16 s3, s4
; CHECK-NEXT: vrintx.f16 q0, q0
; CHECK-NEXT: bx lr
entry:
%0 = tail call <8 x half> @llvm.experimental.constrained.rint.v8f16(<8 x half> %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
Expand All @@ -29,22 +14,7 @@ entry:
define arm_aapcs_vfpcc <8 x half> @test_roundeven_f16(<8 x half> %a) #0 {
; CHECK-LABEL: test_roundeven_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovx.f16 s4, s0
; CHECK-NEXT: vrintn.f16 s0, s0
; CHECK-NEXT: vrintn.f16 s4, s4
; CHECK-NEXT: vins.f16 s0, s4
; CHECK-NEXT: vmovx.f16 s4, s1
; CHECK-NEXT: vrintn.f16 s4, s4
; CHECK-NEXT: vrintn.f16 s1, s1
; CHECK-NEXT: vins.f16 s1, s4
; CHECK-NEXT: vmovx.f16 s4, s2
; CHECK-NEXT: vrintn.f16 s4, s4
; CHECK-NEXT: vrintn.f16 s2, s2
; CHECK-NEXT: vins.f16 s2, s4
; CHECK-NEXT: vmovx.f16 s4, s3
; CHECK-NEXT: vrintn.f16 s4, s4
; CHECK-NEXT: vrintn.f16 s3, s3
; CHECK-NEXT: vins.f16 s3, s4
; CHECK-NEXT: vrintn.f16 q0, q0
; CHECK-NEXT: bx lr
entry:
%0 = tail call <8 x half> @llvm.experimental.constrained.roundeven.v8f16(<8 x half> %a, metadata !"fpexcept.strict")
Expand All @@ -54,22 +24,7 @@ entry:
define arm_aapcs_vfpcc <8 x half> @test_round_f16(<8 x half> %a) #0 {
; CHECK-LABEL: test_round_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovx.f16 s4, s0
; CHECK-NEXT: vrinta.f16 s0, s0
; CHECK-NEXT: vrinta.f16 s4, s4
; CHECK-NEXT: vins.f16 s0, s4
; CHECK-NEXT: vmovx.f16 s4, s1
; CHECK-NEXT: vrinta.f16 s4, s4
; CHECK-NEXT: vrinta.f16 s1, s1
; CHECK-NEXT: vins.f16 s1, s4
; CHECK-NEXT: vmovx.f16 s4, s2
; CHECK-NEXT: vrinta.f16 s4, s4
; CHECK-NEXT: vrinta.f16 s2, s2
; CHECK-NEXT: vins.f16 s2, s4
; CHECK-NEXT: vmovx.f16 s4, s3
; CHECK-NEXT: vrinta.f16 s4, s4
; CHECK-NEXT: vrinta.f16 s3, s3
; CHECK-NEXT: vins.f16 s3, s4
; CHECK-NEXT: vrinta.f16 q0, q0
; CHECK-NEXT: bx lr
entry:
%0 = tail call <8 x half> @llvm.experimental.constrained.round.v8f16(<8 x half> %a, metadata !"fpexcept.strict")
Expand All @@ -79,22 +34,7 @@ entry:
define arm_aapcs_vfpcc <8 x half> @test_trunc_f16(<8 x half> %a) #0 {
; CHECK-LABEL: test_trunc_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovx.f16 s4, s0
; CHECK-NEXT: vrintz.f16 s0, s0
; CHECK-NEXT: vrintz.f16 s4, s4
; CHECK-NEXT: vins.f16 s0, s4
; CHECK-NEXT: vmovx.f16 s4, s1
; CHECK-NEXT: vrintz.f16 s4, s4
; CHECK-NEXT: vrintz.f16 s1, s1
; CHECK-NEXT: vins.f16 s1, s4
; CHECK-NEXT: vmovx.f16 s4, s2
; CHECK-NEXT: vrintz.f16 s4, s4
; CHECK-NEXT: vrintz.f16 s2, s2
; CHECK-NEXT: vins.f16 s2, s4
; CHECK-NEXT: vmovx.f16 s4, s3
; CHECK-NEXT: vrintz.f16 s4, s4
; CHECK-NEXT: vrintz.f16 s3, s3
; CHECK-NEXT: vins.f16 s3, s4
; CHECK-NEXT: vrintz.f16 q0, q0
; CHECK-NEXT: bx lr
entry:
%0 = tail call <8 x half> @llvm.experimental.constrained.trunc.v8f16(<8 x half> %a, metadata !"fpexcept.strict")
Expand All @@ -104,22 +44,7 @@ entry:
define arm_aapcs_vfpcc <8 x half> @test_floor_f16(<8 x half> %a) #0 {
; CHECK-LABEL: test_floor_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovx.f16 s4, s0
; CHECK-NEXT: vrintm.f16 s0, s0
; CHECK-NEXT: vrintm.f16 s4, s4
; CHECK-NEXT: vins.f16 s0, s4
; CHECK-NEXT: vmovx.f16 s4, s1
; CHECK-NEXT: vrintm.f16 s4, s4
; CHECK-NEXT: vrintm.f16 s1, s1
; CHECK-NEXT: vins.f16 s1, s4
; CHECK-NEXT: vmovx.f16 s4, s2
; CHECK-NEXT: vrintm.f16 s4, s4
; CHECK-NEXT: vrintm.f16 s2, s2
; CHECK-NEXT: vins.f16 s2, s4
; CHECK-NEXT: vmovx.f16 s4, s3
; CHECK-NEXT: vrintm.f16 s4, s4
; CHECK-NEXT: vrintm.f16 s3, s3
; CHECK-NEXT: vins.f16 s3, s4
; CHECK-NEXT: vrintm.f16 q0, q0
; CHECK-NEXT: bx lr
entry:
%0 = tail call <8 x half> @llvm.experimental.constrained.floor.v8f16(<8 x half> %a, metadata !"fpexcept.strict")
Expand All @@ -129,22 +54,7 @@ entry:
define arm_aapcs_vfpcc <8 x half> @test_ceil_f16(<8 x half> %a) #0 {
; CHECK-LABEL: test_ceil_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmovx.f16 s4, s0
; CHECK-NEXT: vrintp.f16 s0, s0
; CHECK-NEXT: vrintp.f16 s4, s4
; CHECK-NEXT: vins.f16 s0, s4
; CHECK-NEXT: vmovx.f16 s4, s1
; CHECK-NEXT: vrintp.f16 s4, s4
; CHECK-NEXT: vrintp.f16 s1, s1
; CHECK-NEXT: vins.f16 s1, s4
; CHECK-NEXT: vmovx.f16 s4, s2
; CHECK-NEXT: vrintp.f16 s4, s4
; CHECK-NEXT: vrintp.f16 s2, s2
; CHECK-NEXT: vins.f16 s2, s4
; CHECK-NEXT: vmovx.f16 s4, s3
; CHECK-NEXT: vrintp.f16 s4, s4
; CHECK-NEXT: vrintp.f16 s3, s3
; CHECK-NEXT: vins.f16 s3, s4
; CHECK-NEXT: vrintp.f16 q0, q0
; CHECK-NEXT: bx lr
entry:
%0 = tail call <8 x half> @llvm.experimental.constrained.ceil.v8f16(<8 x half> %a, metadata !"fpexcept.strict")
Expand Down