diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 4004ace444effe..78461bb363ecd4 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -369,12 +369,12 @@ void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) { if (HasMVEFP) { setOperationAction(ISD::FMINNUM, VT, Legal); setOperationAction(ISD::FMAXNUM, VT, Legal); - setOperationAction(ISD::FROUND, VT, Legal); - setOperationAction(ISD::FROUNDEVEN, VT, Legal); - setOperationAction(ISD::FRINT, VT, Legal); - setOperationAction(ISD::FTRUNC, VT, Legal); - setOperationAction(ISD::FFLOOR, VT, Legal); - setOperationAction(ISD::FCEIL, VT, Legal); + for (auto Op : {ISD::FROUND, ISD::STRICT_FROUND, ISD::FROUNDEVEN, + ISD::STRICT_FROUNDEVEN, ISD::FTRUNC, ISD::STRICT_FTRUNC, + ISD::FRINT, ISD::STRICT_FRINT, ISD::FFLOOR, + ISD::STRICT_FFLOOR, ISD::FCEIL, ISD::STRICT_FCEIL}) { + setOperationAction(Op, VT, Legal); + } setOperationAction(ISD::VECREDUCE_FADD, VT, Custom); setOperationAction(ISD::VECREDUCE_FMUL, VT, Custom); setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom); @@ -1350,18 +1350,13 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM_, setOperationAction(ISD::FMAXIMUM, MVT::v4f32, Legal); if (Subtarget->hasV8Ops()) { - setOperationAction(ISD::FFLOOR, MVT::v2f32, Legal); - setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal); - setOperationAction(ISD::FROUND, MVT::v2f32, Legal); - setOperationAction(ISD::FROUND, MVT::v4f32, Legal); - setOperationAction(ISD::FROUNDEVEN, MVT::v2f32, Legal); - setOperationAction(ISD::FROUNDEVEN, MVT::v4f32, Legal); - setOperationAction(ISD::FCEIL, MVT::v2f32, Legal); - setOperationAction(ISD::FCEIL, MVT::v4f32, Legal); - setOperationAction(ISD::FTRUNC, MVT::v2f32, Legal); - setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal); - setOperationAction(ISD::FRINT, MVT::v2f32, Legal); - setOperationAction(ISD::FRINT, MVT::v4f32, Legal); + for (auto Op : {ISD::FROUND, ISD::STRICT_FROUND, ISD::FROUNDEVEN, + ISD::STRICT_FROUNDEVEN, ISD::FTRUNC, ISD::STRICT_FTRUNC, + ISD::FRINT, ISD::STRICT_FRINT, ISD::FFLOOR, + ISD::STRICT_FFLOOR, ISD::FCEIL, ISD::STRICT_FCEIL}) { + setOperationAction(Op, MVT::v2f32, Legal); + setOperationAction(Op, MVT::v4f32, Legal); + } } if (Subtarget->hasFullFP16()) { diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td index 85559c58ad8258..d4b39676b7b4f5 100644 --- a/llvm/lib/Target/ARM/ARMInstrMVE.td +++ b/llvm/lib/Target/ARM/ARMInstrMVE.td @@ -3605,12 +3605,12 @@ multiclass MVE_VRINT_m opcode, } multiclass MVE_VRINT_ops { - defm N : MVE_VRINT_m; - defm X : MVE_VRINT_m; - defm A : MVE_VRINT_m; - defm Z : MVE_VRINT_m; - defm M : MVE_VRINT_m; - defm P : MVE_VRINT_m; + defm N : MVE_VRINT_m; + defm X : MVE_VRINT_m; + defm A : MVE_VRINT_m; + defm Z : MVE_VRINT_m; + defm M : MVE_VRINT_m; + defm P : MVE_VRINT_m; } defm MVE_VRINTf16 : MVE_VRINT_ops; diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td index c512f4e3d6fe0d..462ac8bea45f47 100644 --- a/llvm/lib/Target/ARM/ARMInstrNEON.td +++ b/llvm/lib/Target/ARM/ARMInstrNEON.td @@ -7349,12 +7349,12 @@ multiclass VRINT_FPI op9_7, SDPatternOperator Int> { } } -defm VRINTNN : VRINT_FPI<"n", 0b000, froundeven>; -defm VRINTXN : VRINT_FPI<"x", 0b001, frint>; -defm VRINTAN : VRINT_FPI<"a", 0b010, fround>; -defm VRINTZN : VRINT_FPI<"z", 0b011, ftrunc>; -defm VRINTMN : VRINT_FPI<"m", 0b101, ffloor>; -defm VRINTPN : VRINT_FPI<"p", 0b111, fceil>; +defm VRINTNN : VRINT_FPI<"n", 0b000, any_froundeven>; +defm VRINTXN : VRINT_FPI<"x", 0b001, any_frint>; +defm VRINTAN : VRINT_FPI<"a", 0b010, any_fround>; +defm VRINTZN : VRINT_FPI<"z", 0b011, any_ftrunc>; +defm VRINTMN : VRINT_FPI<"m", 0b101, any_ffloor>; +defm VRINTPN : VRINT_FPI<"p", 0b111, any_fceil>; // Cryptography instructions let PostEncoderMethod = "NEONThumb2DataIPostEncoder", diff --git a/llvm/test/CodeGen/ARM/fp-intrinsics-vector-v8.ll b/llvm/test/CodeGen/ARM/fp-intrinsics-vector-v8.ll index 4840da192c09e3..cb9fcc6eca77b3 100644 --- a/llvm/test/CodeGen/ARM/fp-intrinsics-vector-v8.ll +++ b/llvm/test/CodeGen/ARM/fp-intrinsics-vector-v8.ll @@ -17,11 +17,7 @@ define <4 x float> @nearbyint_v4f32(<4 x float> %x) #0 { define <4 x float> @rint_v4f32(<4 x float> %x) #0 { ; CHECK-LABEL: rint_v4f32: ; CHECK: @ %bb.0: -; CHECK-NEXT: vrintx.f32 s7, s3 -; CHECK-NEXT: vrintx.f32 s6, s2 -; CHECK-NEXT: vrintx.f32 s5, s1 -; CHECK-NEXT: vrintx.f32 s4, s0 -; CHECK-NEXT: vorr q0, q1, q1 +; CHECK-NEXT: vrintx.f32 q0, q0 ; CHECK-NEXT: bx lr %val = call <4 x float> @llvm.experimental.constrained.rint.v4f32(<4 x float> %x, metadata !"round.dynamic", metadata !"fpexcept.strict") ret <4 x float> %val @@ -30,11 +26,7 @@ define <4 x float> @rint_v4f32(<4 x float> %x) #0 { define <4 x float> @round_v4f32(<4 x float> %x) #0 { ; CHECK-LABEL: round_v4f32: ; CHECK: @ %bb.0: -; CHECK-NEXT: vrinta.f32 s7, s3 -; CHECK-NEXT: vrinta.f32 s6, s2 -; CHECK-NEXT: vrinta.f32 s5, s1 -; CHECK-NEXT: vrinta.f32 s4, s0 -; CHECK-NEXT: vorr q0, q1, q1 +; CHECK-NEXT: vrinta.f32 q0, q0 ; CHECK-NEXT: bx lr %val = call <4 x float> @llvm.experimental.constrained.round.v4f32(<4 x float> %x, metadata !"fpexcept.strict") ret <4 x float> %val @@ -43,11 +35,7 @@ define <4 x float> @round_v4f32(<4 x float> %x) #0 { define <4 x float> @roundeven_v4f32(<4 x float> %x) #0 { ; CHECK-LABEL: roundeven_v4f32: ; CHECK: @ %bb.0: -; CHECK-NEXT: vrintn.f32 s7, s3 -; CHECK-NEXT: vrintn.f32 s6, s2 -; CHECK-NEXT: vrintn.f32 s5, s1 -; CHECK-NEXT: vrintn.f32 s4, s0 -; CHECK-NEXT: vorr q0, q1, q1 +; CHECK-NEXT: vrintn.f32 q0, q0 ; CHECK-NEXT: bx lr %val = call <4 x float> @llvm.experimental.constrained.roundeven.v4f32(<4 x float> %x, metadata !"fpexcept.strict") ret <4 x float> %val @@ -56,11 +44,7 @@ define <4 x float> @roundeven_v4f32(<4 x float> %x) #0 { define <4 x float> @floor_v4f32(<4 x float> %x) #0 { ; CHECK-LABEL: floor_v4f32: ; CHECK: @ %bb.0: -; CHECK-NEXT: vrintm.f32 s7, s3 -; CHECK-NEXT: vrintm.f32 s6, s2 -; CHECK-NEXT: vrintm.f32 s5, s1 -; CHECK-NEXT: vrintm.f32 s4, s0 -; CHECK-NEXT: vorr q0, q1, q1 +; CHECK-NEXT: vrintm.f32 q0, q0 ; CHECK-NEXT: bx lr %val = call <4 x float> @llvm.experimental.constrained.floor.v4f32(<4 x float> %x, metadata !"fpexcept.strict") ret <4 x float> %val @@ -69,11 +53,7 @@ define <4 x float> @floor_v4f32(<4 x float> %x) #0 { define <4 x float> @ceil_v4f32(<4 x float> %x) #0 { ; CHECK-LABEL: ceil_v4f32: ; CHECK: @ %bb.0: -; CHECK-NEXT: vrintp.f32 s7, s3 -; CHECK-NEXT: vrintp.f32 s6, s2 -; CHECK-NEXT: vrintp.f32 s5, s1 -; CHECK-NEXT: vrintp.f32 s4, s0 -; CHECK-NEXT: vorr q0, q1, q1 +; CHECK-NEXT: vrintp.f32 q0, q0 ; CHECK-NEXT: bx lr %val = call <4 x float> @llvm.experimental.constrained.ceil.v4f32(<4 x float> %x, metadata !"fpexcept.strict") ret <4 x float> %val diff --git a/llvm/test/CodeGen/Thumb2/mve-strict-round.ll b/llvm/test/CodeGen/Thumb2/mve-strict-round.ll index 2ca7cd41f98c27..33b68a5b4e61c0 100644 --- a/llvm/test/CodeGen/Thumb2/mve-strict-round.ll +++ b/llvm/test/CodeGen/Thumb2/mve-strict-round.ll @@ -4,22 +4,7 @@ define arm_aapcs_vfpcc <8 x half> @test_rint_f16(<8 x half> %a) #0 { ; CHECK-LABEL: test_rint_f16: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmovx.f16 s4, s0 -; CHECK-NEXT: vrintx.f16 s0, s0 -; CHECK-NEXT: vrintx.f16 s4, s4 -; CHECK-NEXT: vins.f16 s0, s4 -; CHECK-NEXT: vmovx.f16 s4, s1 -; CHECK-NEXT: vrintx.f16 s4, s4 -; CHECK-NEXT: vrintx.f16 s1, s1 -; CHECK-NEXT: vins.f16 s1, s4 -; CHECK-NEXT: vmovx.f16 s4, s2 -; CHECK-NEXT: vrintx.f16 s4, s4 -; CHECK-NEXT: vrintx.f16 s2, s2 -; CHECK-NEXT: vins.f16 s2, s4 -; CHECK-NEXT: vmovx.f16 s4, s3 -; CHECK-NEXT: vrintx.f16 s4, s4 -; CHECK-NEXT: vrintx.f16 s3, s3 -; CHECK-NEXT: vins.f16 s3, s4 +; CHECK-NEXT: vrintx.f16 q0, q0 ; CHECK-NEXT: bx lr entry: %0 = tail call <8 x half> @llvm.experimental.constrained.rint.v8f16(<8 x half> %a, metadata !"round.dynamic", metadata !"fpexcept.strict") @@ -29,22 +14,7 @@ entry: define arm_aapcs_vfpcc <8 x half> @test_roundeven_f16(<8 x half> %a) #0 { ; CHECK-LABEL: test_roundeven_f16: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmovx.f16 s4, s0 -; CHECK-NEXT: vrintn.f16 s0, s0 -; CHECK-NEXT: vrintn.f16 s4, s4 -; CHECK-NEXT: vins.f16 s0, s4 -; CHECK-NEXT: vmovx.f16 s4, s1 -; CHECK-NEXT: vrintn.f16 s4, s4 -; CHECK-NEXT: vrintn.f16 s1, s1 -; CHECK-NEXT: vins.f16 s1, s4 -; CHECK-NEXT: vmovx.f16 s4, s2 -; CHECK-NEXT: vrintn.f16 s4, s4 -; CHECK-NEXT: vrintn.f16 s2, s2 -; CHECK-NEXT: vins.f16 s2, s4 -; CHECK-NEXT: vmovx.f16 s4, s3 -; CHECK-NEXT: vrintn.f16 s4, s4 -; CHECK-NEXT: vrintn.f16 s3, s3 -; CHECK-NEXT: vins.f16 s3, s4 +; CHECK-NEXT: vrintn.f16 q0, q0 ; CHECK-NEXT: bx lr entry: %0 = tail call <8 x half> @llvm.experimental.constrained.roundeven.v8f16(<8 x half> %a, metadata !"fpexcept.strict") @@ -54,22 +24,7 @@ entry: define arm_aapcs_vfpcc <8 x half> @test_round_f16(<8 x half> %a) #0 { ; CHECK-LABEL: test_round_f16: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmovx.f16 s4, s0 -; CHECK-NEXT: vrinta.f16 s0, s0 -; CHECK-NEXT: vrinta.f16 s4, s4 -; CHECK-NEXT: vins.f16 s0, s4 -; CHECK-NEXT: vmovx.f16 s4, s1 -; CHECK-NEXT: vrinta.f16 s4, s4 -; CHECK-NEXT: vrinta.f16 s1, s1 -; CHECK-NEXT: vins.f16 s1, s4 -; CHECK-NEXT: vmovx.f16 s4, s2 -; CHECK-NEXT: vrinta.f16 s4, s4 -; CHECK-NEXT: vrinta.f16 s2, s2 -; CHECK-NEXT: vins.f16 s2, s4 -; CHECK-NEXT: vmovx.f16 s4, s3 -; CHECK-NEXT: vrinta.f16 s4, s4 -; CHECK-NEXT: vrinta.f16 s3, s3 -; CHECK-NEXT: vins.f16 s3, s4 +; CHECK-NEXT: vrinta.f16 q0, q0 ; CHECK-NEXT: bx lr entry: %0 = tail call <8 x half> @llvm.experimental.constrained.round.v8f16(<8 x half> %a, metadata !"fpexcept.strict") @@ -79,22 +34,7 @@ entry: define arm_aapcs_vfpcc <8 x half> @test_trunc_f16(<8 x half> %a) #0 { ; CHECK-LABEL: test_trunc_f16: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmovx.f16 s4, s0 -; CHECK-NEXT: vrintz.f16 s0, s0 -; CHECK-NEXT: vrintz.f16 s4, s4 -; CHECK-NEXT: vins.f16 s0, s4 -; CHECK-NEXT: vmovx.f16 s4, s1 -; CHECK-NEXT: vrintz.f16 s4, s4 -; CHECK-NEXT: vrintz.f16 s1, s1 -; CHECK-NEXT: vins.f16 s1, s4 -; CHECK-NEXT: vmovx.f16 s4, s2 -; CHECK-NEXT: vrintz.f16 s4, s4 -; CHECK-NEXT: vrintz.f16 s2, s2 -; CHECK-NEXT: vins.f16 s2, s4 -; CHECK-NEXT: vmovx.f16 s4, s3 -; CHECK-NEXT: vrintz.f16 s4, s4 -; CHECK-NEXT: vrintz.f16 s3, s3 -; CHECK-NEXT: vins.f16 s3, s4 +; CHECK-NEXT: vrintz.f16 q0, q0 ; CHECK-NEXT: bx lr entry: %0 = tail call <8 x half> @llvm.experimental.constrained.trunc.v8f16(<8 x half> %a, metadata !"fpexcept.strict") @@ -104,22 +44,7 @@ entry: define arm_aapcs_vfpcc <8 x half> @test_floor_f16(<8 x half> %a) #0 { ; CHECK-LABEL: test_floor_f16: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmovx.f16 s4, s0 -; CHECK-NEXT: vrintm.f16 s0, s0 -; CHECK-NEXT: vrintm.f16 s4, s4 -; CHECK-NEXT: vins.f16 s0, s4 -; CHECK-NEXT: vmovx.f16 s4, s1 -; CHECK-NEXT: vrintm.f16 s4, s4 -; CHECK-NEXT: vrintm.f16 s1, s1 -; CHECK-NEXT: vins.f16 s1, s4 -; CHECK-NEXT: vmovx.f16 s4, s2 -; CHECK-NEXT: vrintm.f16 s4, s4 -; CHECK-NEXT: vrintm.f16 s2, s2 -; CHECK-NEXT: vins.f16 s2, s4 -; CHECK-NEXT: vmovx.f16 s4, s3 -; CHECK-NEXT: vrintm.f16 s4, s4 -; CHECK-NEXT: vrintm.f16 s3, s3 -; CHECK-NEXT: vins.f16 s3, s4 +; CHECK-NEXT: vrintm.f16 q0, q0 ; CHECK-NEXT: bx lr entry: %0 = tail call <8 x half> @llvm.experimental.constrained.floor.v8f16(<8 x half> %a, metadata !"fpexcept.strict") @@ -129,22 +54,7 @@ entry: define arm_aapcs_vfpcc <8 x half> @test_ceil_f16(<8 x half> %a) #0 { ; CHECK-LABEL: test_ceil_f16: ; CHECK: @ %bb.0: @ %entry -; CHECK-NEXT: vmovx.f16 s4, s0 -; CHECK-NEXT: vrintp.f16 s0, s0 -; CHECK-NEXT: vrintp.f16 s4, s4 -; CHECK-NEXT: vins.f16 s0, s4 -; CHECK-NEXT: vmovx.f16 s4, s1 -; CHECK-NEXT: vrintp.f16 s4, s4 -; CHECK-NEXT: vrintp.f16 s1, s1 -; CHECK-NEXT: vins.f16 s1, s4 -; CHECK-NEXT: vmovx.f16 s4, s2 -; CHECK-NEXT: vrintp.f16 s4, s4 -; CHECK-NEXT: vrintp.f16 s2, s2 -; CHECK-NEXT: vins.f16 s2, s4 -; CHECK-NEXT: vmovx.f16 s4, s3 -; CHECK-NEXT: vrintp.f16 s4, s4 -; CHECK-NEXT: vrintp.f16 s3, s3 -; CHECK-NEXT: vins.f16 s3, s4 +; CHECK-NEXT: vrintp.f16 q0, q0 ; CHECK-NEXT: bx lr entry: %0 = tail call <8 x half> @llvm.experimental.constrained.ceil.v8f16(<8 x half> %a, metadata !"fpexcept.strict")