SelectionDAG: Improve expandFMINIMUM_FMAXIMUM#137367
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SelectionDAG: Improve expandFMINIMUM_FMAXIMUM#137367
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@llvm/pr-subscribers-backend-mips @llvm/pr-subscribers-llvm-selectiondag Author: YunQiang Su (wzssyqa) ChangesISD::FMAXNUM and ISD::FMINNUM treat +0.0>-0.0 now, so let's set MinMaxMustRespectOrderedZero for it. Full diff: https://github.com/llvm/llvm-project/pull/137367.diff 1 Files Affected:
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 6930b54ddb14a..7baed2d591514 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -8573,8 +8573,6 @@ SDValue TargetLowering::expandFMINIMUM_FMAXIMUM(SDNode *N,
unsigned CompOpcIeee = IsMax ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE;
unsigned CompOpc = IsMax ? ISD::FMAXNUM : ISD::FMINNUM;
- // FIXME: We should probably define fminnum/fmaxnum variants with correct
- // signed zero behavior.
bool MinMaxMustRespectOrderedZero = false;
if (isOperationLegalOrCustom(CompOpcIeee, VT)) {
@@ -8582,6 +8580,7 @@ SDValue TargetLowering::expandFMINIMUM_FMAXIMUM(SDNode *N,
MinMaxMustRespectOrderedZero = true;
} else if (isOperationLegalOrCustom(CompOpc, VT)) {
MinMax = DAG.getNode(CompOpc, DL, VT, LHS, RHS, Flags);
+ MinMaxMustRespectOrderedZero = true;
} else {
if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT))
return DAG.UnrollVectorOp(N);
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See：#168838 |
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This was reverted, and the contentious part is signaling nan handling. One of the reasons simply reverting this is wrong is the signed zero behavior should remain regardless of that |
ISD::FMAXNUM and ISD::FMINNUM treat +0.0>-0.0 now, so let's set MinMaxMustRespectOrderedZero for it.
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🐧 Linux x64 Test Results
Failed Tests(click on a test name to see its output) LLVMLLVM.CodeGen/NVPTX/atomicrmw-sm60.llLLVM.CodeGen/NVPTX/atomicrmw-sm70.llLLVM.CodeGen/NVPTX/atomicrmw-sm90.llLLVM.CodeGen/PowerPC/fminimum-fmaximum.llLLVM.CodeGen/X86/fminimum-fmaximum.llIf these failures are unrelated to your changes (for example tests are broken or flaky at HEAD), please open an issue at https://github.com/llvm/llvm-project/issues and add the |
arsenm
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arsenm
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Globalisel presumably needs the same change
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@arsenm MinMaxMustRespectOrderedZero is not set here.
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@arsenm MinMaxMustRespectOrderedZero is used to skip it if we have minmax OPCs.
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| EVT IntVT = VT.changeTypeToInteger(); | ||
| SDValue NTrunc = N; | ||
| if (!TLI.isTypeLegal(IntVT)) { | ||
| EVT FloatVT = VT.changeElementType(MVT::f32); |
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Hardcoding this to i32/f32 doesn't feel right. Can you find the next smallest FP legal FP type?
Co-authored-by: Matt Arsenault <arsenm2@gmail.com>
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This PR introduces performance regression on some architectures. So Let's split into some small patches. |
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See: #180487 |
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We try the Legal ones first and then Custom ones then.
determineFloatSign, which return the SDValue to determine the Sign of a SDValue.