[SYCL][FPGA] Prepare future implementation of experimental pipe properties

[pcolberg]

Add a template parameter to pass compile-time constant properties to
sycl::ext::intel::experimental::pipe, and redeclare pipe implementation
as a specialization when the properties list is empty; otherwise, when
the properties list is non-empty, throw a descriptive compiler error.

The unnamed template parameter allows implementation of the case where
the properties list is non-empty in a downstream, FPGA-specific header,
before finalizing pipe properties for inclusion into this header.

See draft specification in #5839

@GarveyJoe @rho180 @sherry-yuan @bsyrowik @tiwaria1 @ajaykumarkannan

[pcolberg]

Same unrelated test failures as outlined in #5766 (comment).

[gmlueck]

This does not match the current wording in the draft specification #5839, but it is in line with our offline discussions. I have no concerns with this PR, but someone from the implementation team should review.

[pcolberg]

Hi @intel/llvm-reviewers-runtime, since @cperkinsintel is unavailable for review, it would be great if you could take over the review in time for the next release.

[pcolberg]

@intel/llvm-reviewers-runtime could you take a quick look to ensure this gets in before code complete?

[s-kanaev]

LGTM

[pcolberg]

Thanks @s-kanaev and @steffenlarsen for the quick review 🙂

@intel/llvm-gatekeepers could you merge in time for code complete?

[bader]

@intel/dpcpp-esimd-reviewers, FYI. 4 failing tests are failing on ESIMD emulator - https://github.com/intel/llvm/runs/5685843530?check_suite_focus=true. I don't think these failures are related to this PR, so I'm going to merge it.