SP-M3: mixed-signal analog+digital on shared map/fold substrate (verilog.dag digital side)

[briansrls]

Auto-opened by session-dashboard for session sharp-ibex-559.
Pushing to session/sharp-ibex-559 advances this PR.

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[gunbai-bot]

Review feedback addressed @ 96ec0ab8f9 (fierce-ibex-308)

Finding (claude #29564 / cursor #29574)	Fix
LogicLevel parallel to Bool without disposition	Fixed — 🟡 gated mark naming Verilog 4-state (0/1/X/Z) trigger; kept distinct 2-state carrier until X/Z witnesses enroll
Unused DigitalSample / DigitalSignal / List import	Fixed — deleted forward scaffold (no consumers in PR)
Hand-rolled circuit_primitive_kind_eq in verilog.dag	Fixed — moved to circuit_step.dag colocated with CircuitPrimitiveKind; uses discriminant(v: left) == discriminant(v: right)
Hand-rolled logic_level_eq arm matrix	Fixed — discriminant-based equality (Practice 10)

Witness mixed_signal_map_fold_anchor updated to import circuit_primitive_kind_eq from circuit_step. Mixed-signal map/fold teeth unchanged.

Fresh api-review + CI needed on new HEAD.

— sent from fierce-ibex-308

[gunbai-bot]

cursor/composer-2.5 REQUEST_CHANGES (#29574) — already addressed @ 96ec0ab8f9, no further code change

Review artifact timestamp 23:22Z predates fix commit 96ec0ab8f9 (23:36Z). Verified both findings against current HEAD:

1. circuit_primitive_kind_eq hand-arm matrix in verilog.dag — fixed

• Removed from verilog.dag (review line :899 now verilog_identifier_pattern, not the eq helper).
• Canonical home: src/v4/std/circuit_step.dag:18-23 — discriminant(v: left) == discriminant(v: right) on CircuitPrimitiveKind.
• Consumers: mixed_signal_map_fold_anchor.dag imports circuit_primitive_kind_eq from v4.std.circuit_step (Practice 5 concept-home).

2. logic_level_eq hand-arm matrix — fixed

• verilog.dag:877-879 — logic_level_eq now uses discriminant(v: left) == discriminant(v: right), not per-arm match.
• LogicLevel carries 🟡 disposition (feature:verilog-4state-logic-level) at :807-809; predicate uses canonical discriminant surface per Practice 10.

No hand-rolled coproduct equality helpers remain on the changed substrate. Please re-review on 96ec0ab8f9.

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[gunbai-bot]

claude/claude-opus-4-7 APPROVE (#29599) — verified @ 96ec0ab8f9, no code change

Verdict: APPROVE accepted.

Verified @ HEAD 96ec0ab8f9:

• CircuitPrimitiveKind lifted to src/v4/std/circuit_step.dag (no parallel def in timeseries_signal.dag); consumer imports updated
• circuit_primitive_kind_eq uses canonical discriminant surface (circuit_step.dag:18-23)
• LogicLevel coproduct with 🟡 feature:verilog-4state-logic-level; logic_level_eq discriminant-based (verilog.dag:877-879)
• and_combinational_map_step / d_flipflop_fold_step pure data + free functions
• mixed_signal_map_fold_anchor.dag exercises analog+digital through shared circuit_primitive_kind_eq
• No hand-Rust; no corpus runner diff (not a corpus-toucher)

Merge readiness: Awaiting cursor re-APPROVE after #29574 fix + green CI. Not subject to corpus PARK.

— sent from fierce-ibex-308

[gunbai-bot]

cursor/composer-2.5 APPROVE (#29600) — verified @ 96ec0ab8f9, no code change

Verdict: APPROVE accepted; Findings: None — prior #29574 feedback addressed on this HEAD.

Verified @ 96ec0ab8f9:

• CircuitPrimitiveKind single authority in circuit_step.dag; circuit_primitive_kind_eq discriminant-based (:18-23)
• logic_level_eq discriminant-based (verilog.dag:877-879); LogicLevel 🟡 gated (:807-809)
• Digital map/fold step operators; dead DigitalSample/DigitalSignal scaffold removed
• mixed_signal_map_fold_anchor.dag cross-domain witness; no corpus runner diff
• v4 .dag only (P5 N/A)

Merge readiness @ 96ec0ab8f9: ≥2 distinct api-review APPROVE met (cursor #29600 + claude #29599); no open REQUEST_CHANGES; MERGEABLE. CI pending on 27583512914 — operator merge when green (not corpus PARK).

— sent from fierce-ibex-308

[gunbai-bot]

CI fix @ 620ad87ec8

Root cause: ci job (modeled one-binary floor) failed in gate-3 batch-executor --perturb-check walk with claim_executor: unknown argument: --perturb-check (trailing ' is log-capture artifact from printf wrapping). Gate-3 preflight built gunbc/ci-claim-gate/claim_batch but not claim_executor; restored target/ cache held a stale pre-#4950 binary without the walk-halt flag.

Fix:

1. Rebased onto current main (one-binary CI + gate-3 script from Finish ci_runner.dag as the one-binary CI floor + collapse ci.yml shim (LOAD-BEARING; design-sign-first; AWAIT full mandate message from zesty-swift-79 before acting) #4960/ci(dissolution): collapse pure ci-claim-gate wrapper scripts into gate-3 #5012).
2. ci_runner.dag: ensure_claim_executor_binary() — always cargo build --bin claim_executor before gate-3.

— sent from fierce-ibex-308

[gunbai-bot]

claude #29641 APPROVE — verified @ 620ad87ec8, no code change

Verdict: APPROVE accepted — findings none on substrate slice.

#29641 claim	@ 620ad87ec8
Shared CircuitPrimitiveKind in std/circuit_step.dag	✓ (MapStep/FoldStep/SolveStep coproduct)
timeseries_signal + verilog import shared kind	✓
Analog R/L/C map/fold + digital AND/DFF on shared substrate	✓ (verilog.dag:830-874, timeseries_signal.dag)
LogicLevel declared coproduct + 🟡 feature:verilog-4state-logic-level	✓ (verilog.dag:807-812)
Equality via discriminant (no hand is_* predicates)	✓ (circuit_primitive_kind_eq, logic_level_eq)
Manual anchor exercises both lanes	✓ (mixed_signal_map_fold_anchor.dag)
ci_runner.dag rebuilds claim_executor for gate-3	✓ (ensure_claim_executor_binary)
No hand-Rust / no src/v3/	✓

Separate blocker (not this review): cursor #29642 REQUEST_CHANGES on same HEAD flags claim-row schema drift in mixed_signal_map_fold_anchor.dag (unit vs layer, anchor key shape) — tracked for fix; does not invalidate substrate APPROVE.

Merge readiness @ 620ad87ec8: claude APPROVE ✓; cursor #29642 REQUEST_CHANGES open ❌; CI 27586346580 pending ❌.

— sent from fierce-ibex-308

[gunbai-bot]

Operator teardown directive (bold-crane/smart-hawk-763): winding P4 SPICE swarm down. PR closed per lane manager archive pass — not abandoned, superseded by operator wind-down.