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Rejected valid signal name #2076

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matlupi opened this issue Jan 19, 2024 · 4 comments · May be fixed by #2102
Open

Rejected valid signal name #2076

matlupi opened this issue Jan 19, 2024 · 4 comments · May be fixed by #2102
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rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017).

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@matlupi
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matlupi commented Jan 19, 2024

Describe the bug

Short summary.

To Reproduce

verible-verilog-lint test.sv

with test.sv

module test;
  logic analog;
endmodule

Actual behavior:

Rejects valid syntax

test.sv:2 9-14 syntax error at token "analog"

Expected behavior

No syntax error.
analog is not a reserved keyword according to LRM Annex B Table B.1
@matlupi matlupi added the rejects-valid syntax If the parser wrongly rejects syntactically valid code (according to SV-2017). label Jan 19, 2024
@hzeller
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hzeller commented Jan 31, 2024

Yeah, this is because we accept a few more potential keywords from Verilog-AMS

We should probably add that to the 'keyword or identifier' classification like here

verible/verilog/parser/verilog.y

Lines 757 to 782 in c548dbb

KeywordIdentifier
/* The following are keywords in certain dialects of Verilog.
* These are used in some contexts, but in others we just regard them as
* regular identifiers.
* TODO(hzeller): Often, SymbolIdentifier is used in direct token
* comparisons in the code. They should match GenericIdentifier instead.
*/
/* Verilog-AMS: */
: TK_access
{ $$ = std::move($1); }
| TK_exclude
{ $$ = std::move($1); }
| TK_flow
{ $$ = std::move($1); }
| TK_from
{ $$ = std::move($1); }
| TK_discrete
{ $$ = std::move($1); }
/* TK_sample is in SystemVerilog coverage_event */
| TK_sample
{ $$ = std::move($1); }
| TK_infinite
{ $$ = std::move($1); }
| TK_continuous
{ $$ = std::move($1); }
;

@matlupi
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matlupi commented Feb 1, 2024

Is there a switch to avoid this syntax error?
Since the file is not a VAMS file, I should be able to get around that, right?

@hzeller
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hzeller commented Feb 1, 2024

Unfortunately not currently. We do have an issu #141 to allow switching Verilog dialects, but it is yet to be picked up by someone.

But if you make a pull request that adds the keyword to the section I mentioned, it should fix your issue.

@matlupi
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matlupi commented Feb 2, 2024

Will do, thanks!

matlupi pushed a commit to matlupi/verible that referenced this issue Feb 6, 2024
ML fixed chipsalliance#2076
ec40eb0
@matlupi matlupi linked a pull request Feb 6, 2024 that will close this issue
Open
matlupi pushed a commit to matlupi/verible that referenced this issue Feb 6, 2024
ML added testcase for chipsalliance#2076
53413c2
matlupi pushed a commit to matlupi/verible that referenced this issue Sep 25, 2024
ML fixed chipsalliance#2076
f287035
matlupi pushed a commit to matlupi/verible that referenced this issue Sep 25, 2024
ML added testcase for chipsalliance#2076
72ff5ce
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Resolve "Rejected valid signal name" matlupi/verible
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@hzeller @matlupi