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Migrate name style rules to regex #2074

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IEncinas10 opened this issue Jan 13, 2024 · 4 comments
Open
10 tasks

Migrate name style rules to regex #2074

IEncinas10 opened this issue Jan 13, 2024 · 4 comments
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enhancement New feature or request style-linter Verilog style-linter issues

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@IEncinas10
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IEncinas10 commented Jan 13, 2024

There are several "name style rules" and one more being developed (#1983) which have their rules hardcoded or with small configuration capabilities.

In the past, this motivated a PR that eventually didn't land but did the same thing (using std::regex which seemed to be the problem). The topic was raised again in #2017.

This is a "macro issue" to track the conversion of the existing rules to be regex-based (using re2). I'll keep this in mind and work on it on spare time, I don't know if I'll tackle this on a per-rule bases or I'll group various rules on the same PR.

  • constraint_name_style
  • enum_name_style
  • interface_name_style
  • macro_name_style
  • parameter_name_style
  • parameter_type_name_style
  • signal_name_style
  • struct_union_name_style
  • port_name_suffix
  • ¿dff_name_style? (if it lands)

If anyone comes by this issue and wants to help feel free to do so 😃

@IEncinas10 IEncinas10 added enhancement New feature or request style-linter Verilog style-linter issues labels Jan 13, 2024
@IEncinas10 IEncinas10 self-assigned this Jan 13, 2024
@sconwayaus
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Can you add port_name_suffix to the list too. It's basically the same (checks style (snake_case) with some prefixes), and needs some configuration. Regex looks like a good answer.

Happy to with this one too.

@IEncinas10
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Missed this one, thanks!

@sconwayaus
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Happy to help out with any of these rules too.

I've already been playing with the port_name_suffix rule before I saw this issue, and added configuration to it. Just need to convert this over to regex (add tests, etc...).

@burnfield
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Would be awesome. This has been implemented in svlint, if you're looking for inspiration.

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enhancement New feature or request style-linter Verilog style-linter issues
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