linter: Add forbid-implicit-declarations rule

Signed-off-by: Lukasz Dalek <[email protected]>

verilog/analysis/checkers/BUILD

@@ -29,6 +29,7 @@ cc_library(
         ":explicit_task_lifetime_rule",
         ":forbid_consecutive_null_statements_rule",
         ":forbid_defparam_rule",
+        ":forbid_implicit_declarations_rule",
         ":forbidden_anonymous_enums_rule",
         ":forbidden_anonymous_structs_unions_rule",
         ":forbidden_macro_rule",
@@ -354,6 +355,47 @@ cc_test(
     ],
 )
 
+cc_library(
+    name = "forbid_implicit_declarations_rule",
+    srcs = ["forbid_implicit_declarations_rule.cc"],
+    hdrs = ["forbid_implicit_declarations_rule.h"],
+    deps = [
+        "//common/analysis:citation",
+        "//common/analysis:lint_rule_status",
+        "//common/analysis:text_structure_lint_rule",
+        "//common/analysis/matcher",
+        "//common/analysis/matcher:bound_symbol_manager",
+        "//common/analysis/matcher:core_matchers",
+        "//common/analysis/matcher:matcher_builders",
+        "//common/text:symbol",
+        "//common/text:tree_context_visitor",
+        "//common/util:auto_pop_stack",
+        "//verilog/CST:identifier",
+        "//verilog/CST:verilog_matchers",
+        "//verilog/analysis:descriptions",
+        "//verilog/analysis:lint_rule_registry",
+        "//verilog/analysis:symbol_table",
+        "//verilog/analysis:verilog_project",
+        "@com_google_absl//absl/strings",
+    ],
+    alwayslink = 1,
+)
+
+cc_test(
+    name = "forbid_implicit_declarations_rule_test",
+    srcs = ["forbid_implicit_declarations_rule_test.cc"],
+    deps = [
+        ":forbid_implicit_declarations_rule",
+        "//common/analysis:linter_test_utils",
+        "//common/analysis:text_structure_linter_test_utils",
+        "//common/text:symbol",
+        "//verilog/CST:verilog_nonterminals",
+        "//verilog/CST:verilog_treebuilder_utils",
+        "//verilog/analysis:verilog_analyzer",
+        "@com_google_googletest//:gtest_main",
+    ],
+)
+
 cc_library(
     name = "mismatched_labels_rule",
     srcs = ["mismatched_labels_rule.cc"],

verilog/analysis/default_rules.h

@@ -69,6 +69,7 @@ constexpr const char* kDefaultRuleSet[] = {
     // TODO(b/117131903): "proper-parameter-declaration",
     // TODO(b/131637160): "signal-name-style",
     // TODO(b/120784977): "numeric-format-string-style",
+    // TODO(b/138353038): "forbid-implicit-declaration",
     // TODO: "one-module-per-file",
     // TODO: "banned-declared-name-patterns",
     // "endif-comment",

verilog/tools/lint/BUILD

@@ -30,6 +30,7 @@ _linter_test_configs = [
     ("explicit-parameter-storage-type", "explicit_parameter_storage_type", True),
     ("explicit-task-lifetime", "explicit_task_lifetime", True),
     ("forbid-consecutive-null-statements", "forbid_consecutive_null_statements", True),
+    ("forbid-implicit-declarations", "forbid_implicit_declarations", False),
     ("forbid-line-continuations", "forbid_line_continuations", True),
     ("generate-label", "generate_label_module", True),
     ("generate-label", "generate-label-module-body", True),  # uses parse directive

verilog/tools/lint/testdata/always_comb_blocking.sv

@@ -1,4 +1,6 @@
 module always_comb_blocking;
+  wire a;
+
   always_comb
     a <= b; // [Style: combinational-logic] [always-comb-blocking]
 endmodule

verilog/tools/lint/testdata/always_comb_module.sv

@@ -1,4 +1,6 @@
 module always_comb_module;
+  wire a;
+
   always @* begin
     a = b + c;
   end

verilog/tools/lint/testdata/always_ff_non_blocking.sv

@@ -1,4 +1,6 @@
 module always_ff_non_blocking;
+  wire a;
+
   always_ff @(posedge c)
     a = b; // [Style: sequential-logic] [always-ff-non-blocking]
 endmodule

verilog/tools/lint/testdata/generate_begin_module.sv

@@ -1,6 +1,8 @@
 module generate_begin_module;
   // verilog_lint: waive legacy-generate-region
   generate
+    wire foo;
+
     begin : gen_block1
       always @(posedge clk) foo <= bar;
     end

verilog/tools/lint/testdata/object_creation_name.sv

@@ -1,4 +1,6 @@
 module object_creation_name;
+  wire cool_driver_h;
+
   initial begin
     // This is good
     cool_driver_h = cool_driver::type_id::create("cool_driver_h", this);

verilog/tools/lint/testdata/suggest_parentheses_example.sv

@@ -1,3 +1,5 @@
 module suggest_parentheses_example;
+  wire foo;
+
   assign foo = condition_a? condition_b? a : b : c;
 endmodule