Fixing various issues reported by mglb

chipsalliance · Aug 12, 2022 · 18e990c · 18e990c
1 parent 48abc7b
commit 18e990c
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Showing 5 changed files with 17 additions and 22 deletions.
diff --git a/common/util/cmd_positional_arguments.cc b/common/util/cmd_positional_arguments.cc
@@ -44,19 +44,18 @@ absl::Status CmdPositionalArguments::SetIncludeDir(
 }
 
 // Gets include directories arguments.
-std::vector<absl::string_view> CmdPositionalArguments::GetIncludeDirs() {
+std::vector<absl::string_view> CmdPositionalArguments::GetIncludeDirs() const {
   return include_dirs_;
 }
 
-std::vector<std::pair<absl::string_view, absl::string_view>>
-
 // Gets macro defines arguments.
-CmdPositionalArguments::GetDefines() {
+std::vector<std::pair<absl::string_view, absl::string_view>>
+CmdPositionalArguments::GetDefines() const {
   return defines_;
 }
 
 // Gets SV files arguments.
-std::vector<absl::string_view> CmdPositionalArguments::GetFiles() {
+std::vector<absl::string_view> CmdPositionalArguments::GetFiles() const {
   return files_;
 }
 

diff --git a/common/util/cmd_positional_arguments.h b/common/util/cmd_positional_arguments.h
@@ -1,4 +1,4 @@
-// Copyright 2017-2020 The Verible Authors.
+// Copyright 2017-2022 The Verible Authors.
 //
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
@@ -32,13 +32,14 @@ class CmdPositionalArguments {
   absl::Status ParseArgs();
 
   // Gets include directories arguments.
-  std::vector<absl::string_view> GetIncludeDirs();
+  std::vector<absl::string_view> GetIncludeDirs() const;
 
   // Gets macro defines arguments.
-  std::vector<std::pair<absl::string_view, absl::string_view>> GetDefines();
+  std::vector<std::pair<absl::string_view, absl::string_view>> GetDefines()
+      const;
 
   // Gets SV files arguments.
-  std::vector<absl::string_view> GetFiles();
+  std::vector<absl::string_view> GetFiles() const;
 
  private:
   // Sets a include directory argument.

diff --git a/verilog/preprocessor/verilog_preprocess.cc b/verilog/preprocessor/verilog_preprocess.cc
@@ -463,12 +463,14 @@ absl::Status VerilogPreprocess::HandleDefine(
 
   // Parsing showed that things are syntatically correct.
   // But let's only emit things if we're in an active preprocessing branch.
-  if (conditional_block_.top().InSelectedBranch() && config_.forward_define) {
+  if (conditional_block_.top().InSelectedBranch()) {
     RegisterMacroDefinition(macro_definition);
 
     // For now, forward all definition tokens.
-    for (const auto& token : define_tokens) {
-      preprocess_data_.preprocessed_token_stream.push_back(token);
+    if (config_.forward_define) {
+      for (const auto& token : define_tokens) {
+        preprocess_data_.preprocessed_token_stream.push_back(token);
+      }
     }
   }
 

diff --git a/verilog/tools/preprocessor/verilog_preprocessor.cc b/verilog/tools/preprocessor/verilog_preprocessor.cc
@@ -168,7 +168,7 @@ static absl::Status GenerateVariants(absl::string_view source_file,
   // Printing the token streams of every possible variant.
   int variants_counter = 1;
   for (const auto& current_variant : control_flow_tree.variants_) {
-    outs << "Variant number " << variants_counter++ << ":\n";
+    outs << "//////// variant: " << variants_counter++ << "////////:\n";
     for (auto token : current_variant) outs << token.text();
     puts("");
   }
@@ -185,14 +185,7 @@ ABSL_FLAG(bool, generate_variants, false,
 
 int main(int argc, char* argv[]) {
   const std::string usage =
-      absl::StrCat("usage:\n", argv[0], " [options] file [<file>...]\n\n",
-                   "options summary:\n",
-                   "-multiple_cu: Files are preprocessed in separate "
-                   "compilation units.\n",
-                   "-strip_comments: Replaces one/multi-line comments with "
-                   "equal white-spaces.\n",
-                   "-generate_variants: Generates every possible variants "
-                   "w.r.t. compiler conditionals.\n");
+      absl::StrCat("usage:\n", argv[0], " [options] file [<file>...]\n");
 
   // Process invocation args.
   const auto args = verible::InitCommandLine(usage, &argc, &argv);

diff --git a/verilog/tools/preprocessor/verilog_preprocessor_test.sh b/verilog/tools/preprocessor/verilog_preprocessor_test.sh
@@ -53,7 +53,7 @@ preprocessor="$(rlocation ${TEST_WORKSPACE}/$1)"
 ################################################################################
 echo "=== Test the 'help' command."
 
-"$preprocessor" --help > "$MY_OUTPUT_FILE" 2>&1
+"$preprocessor" --helpfull > "$MY_OUTPUT_FILE" 2>&1
 
 # status="$?"
 # [[ $status == 0 ]] || {