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UCCL: Simplify and Optimize for batch transfers - #1271

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ovidiusm merged 47 commits into
ai-dynamo:mainfrom
praveingk:one_sided_async
Mar 1, 2026
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UCCL: Simplify and Optimize for batch transfers#1271
ovidiusm merged 47 commits into
ai-dynamo:mainfrom
praveingk:one_sided_async

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@praveingk

@praveingk praveingk commented Feb 3, 2026 •
edited by coderabbitai Bot
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What?

  1. Simplified logic by using just one-sided operations for both read/write. This reduces the prep time significantly.
  2. Use vector read/write operation which internally submits operations to a task ring. This improves the bandwidth and latency for posting the transfers.

Before (Performance for batched operations)

----------------------------------------------------------------------------------------------------------------------------------------------------------------

Block Size (B)      Batch Size     B/W (GB/Sec)   Avg Lat. (us)  Avg Prep (us)  P99 Prep (us)  Avg Post (us)  P99 Post (us)  Avg Tx (us)    P99 Tx (us)
----------------------------------------------------------------------------------------------------------------------------------------------------------------
4096                10000          0.695738       5.9            14758.0        14758.0        52938.4        53446.0        5919.6         6010.0
8192                10000          1.240937       6.6            33968.0        33968.0        59379.2        60460.0        6601.7         6716.0
16384               10000          2.121422       7.7            36645.0        36645.0        69396.1        74834.0        7798.8         7979.0
32768               10000          3.611707       9.1            12306.0        12306.0        81523.3        82027.0        9191.7         9345.0
65536               10000          5.585293       11.7           12671.0        12671.0        105434.5       114810.0       11889.6        12085.0
131072              10000          7.573363       17.3           38601.0        38601.0        155376.3       159620.0       17655.1        17820.0
262144              10000          9.210084       28.5           13269.0        13269.0        255454.2       263371.0       29159.7        29389.0
524288              10000          10.392007      50.5           36123.0        36123.0        452768.2       459926.0       51706.7        52083.0

After (Performance for batched operations)

----------------------------------------------------------------------------------------------------------------------------------------------------------------

Block Size (B)      Batch Size     B/W (GB/Sec)   Avg Lat. (us)  Avg Prep (us)  P99 Prep (us)  Avg Post (us)  P99 Post (us)  Avg Tx (us)    P99 Tx (us)
----------------------------------------------------------------------------------------------------------------------------------------------------------------
4096                10000          3.163283       1.3            3045.0         3045.0         1416.7         1640.0         11528.8        12381.0
8192                10000          5.727470       1.4            4663.0         4663.0         1461.9         1691.0         12836.5        13002.0
16384               10000          8.629974       1.9            3077.0         3077.0         1459.7         1691.0         17522.2        17985.0
32768               10000          11.816224      2.8            3405.0         3405.0         1435.8         1688.0         26292.2        26370.0
65536               10000          12.232887      5.4            2991.0         2991.0         1459.6         1808.0         52111.0        52409.0
131072              10000          12.432499      10.5           2969.0         2969.0         1448.1         1697.0         103975.9       103992.0
262144              10000          12.533264      20.9           2993.0         2993.0         1471.4         1761.0         207684.2       207747.0
524288              10000          12.581106      41.7           2818.0         2818.0         1477.3         1707.0         415246.3       415348.0

Why?

Justification for the PR. If there is an existing issue/bug, please reference it. For
bug fixes, the 'Why?' and 'What?' can be merged into a single item.

How?

It is optional, but for complex PRs, please provide information about the design,
architecture, approach, etc.

Summary by CodeRabbit

  • Documentation

    • Updated UCCL plugin guidance about RDMA/read mode and refreshed roadmap with status markers.

  • Improvements

    • Simplified read behavior and transfer handling for the UCCL connector.
    • More robust backend shutdown and listener lifecycle.
    • Streamlined batch transfer processing and improved hex-formatted logging and metadata handling.
    • Minor destructor/resource cleanup for a benchmark worker.

  • Tests

    • Removed special RC-mode activation for read operations in UCCL tests.

  • Chores

    • Updated CI/build identifiers and scripts.

@praveingk
Add support to prepare Fifo
90ed9db 
Signed-off-by: Pravein Govindan Kannan <pravein.govindan.kannan@ibm.com>
@praveingk
Fix errors
8a354ea 
Signed-off-by: Pravein Govindan Kannan <pravein.govindan.kannan@ibm.com>
@praveingk
Add vector read/write support
a9bcd2b 
Signed-off-by: Pravein Govindan Kannan <pravein.govindan.kannan@ibm.com>
@praveingk
Use prepare fifo APIs
8fd6a22 
Signed-off-by: Pravein Govindan Kannan <pravein.govindan.kannan@ibm.com>
@praveingk
Remove RCMODE
897f437 
Signed-off-by: Pravein Govindan Kannan <pravein.govindan.kannan@ibm.com>
@praveingk
Remove rcmode in prepXfer
5921a68 
Signed-off-by: Pravein Govindan Kannan <pravein.govindan.kannan@ibm.com>
@praveingk
Remove rcmode from CI
f03ee88 
Signed-off-by: Pravein Govindan Kannan <pravein.govindan.kannan@ibm.com>
@praveingk
Fix cleanup
76f8c81 
Signed-off-by: Pravein Govindan Kannan <pravein.govindan.kannan@ibm.com>
@praveingk
Maintain a single transfer ID
e80c85b 
Signed-off-by: Pravein Govindan Kannan <pravein.govindan.kannan@ibm.com>
@praveingk
Fix formatting
047fd3c 
Signed-off-by: Pravein Govindan Kannan <pravein.govindan.kannan@ibm.com>
@praveingk
Fix formatting after changes
0438400 
Signed-off-by: Pravein Govindan Kannan <pravein.govindan.kannan@ibm.com>
@praveingk
Remove redundant FIFO_ITEM_SIZE
83a8eea 
Signed-off-by: Pravein Govindan Kannan <pravein.govindan.kannan@ibm.com>
@praveingk
Update commit SHA of UCCL
d70747d 
Signed-off-by: Pravein Govindan Kannan <pravein.govindan.kannan@ibm.com>
@praveingk
Remove unused variable
92f0466 
Signed-off-by: Pravein Govindan Kannan <pravein.govindan.kannan@ibm.com>
@praveingk
Remove unused vars
d276d72 
Signed-off-by: Pravein Govindan Kannan <pravein.govindan.kannan@ibm.com>
@praveingk
Fix error
800179b 
Signed-off-by: Pravein Govindan Kannan <pravein.govindan.kannan@ibm.com>
@praveingk
Add recent updates to README
be118d1 
Signed-off-by: Pravein Govindan Kannan <pravein.govindan.kannan@ibm.com>
@praveingk
praveingk requested a review from a team as a code owner February 3, 2026 10:16
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@github-actions

github-actions Bot commented Feb 3, 2026

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👋 Hi praveingk! Thank you for contributing to ai-dynamo/nixl.

Your PR reviewers will review your contribution then trigger the CI to test your changes.

🚀

@praveingk
Merge branch 'main' into one_sided_async
2f94415 
Signed-off-by: Pravein Govindan Kannan <pravein.govindan.kannan@ibm.com>
@praveingk
Fix copyright and format
dc3d822 
Signed-off-by: Pravein Govindan Kannan <pravein.govindan.kannan@ibm.com>
@praveingk
Merge branch 'one_sided_async' of github.com:praveingk/nixl into one_…
c24e886 
…sided_async
@brminich

brminich commented Feb 3, 2026

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/ok to test c24e886

@brminich

brminich commented Feb 3, 2026

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/build

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@svc-nixl svc-nixl mentioned this pull request Aug 5, 2026
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@coderabbitai coderabbitai[bot] coderabbitai[bot] left review comments
@brminich brminich brminich approved these changes
@dpressle dpressle dpressle approved these changes
@isdrk isdrk isdrk approved these changes
@ovidiusm ovidiusm ovidiusm approved these changes
@aranadive aranadive Awaiting requested review from aranadive aranadive is a code owner

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@praveingk @brminich @isdrk @dpressle @ovidiusm