Changing sgpr limits#2184
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KKyang
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AlexBrownAMD
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AlexBrownAMD
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| # Use VGPR up to next occupancy threshold: | ||
| maxVgprs, occupancy = self.getMaxRegsForOccupancy(kernel["NumThreads"], self.vgprPool.size(), self.sgprPool.size(), \ | ||
| # Account for additional temp sgprs that will be required for code gen, up to physical limits. +5 approximates upper end of required temp space for GSU sync | ||
| requiredSgprs = min(self.sgprPool.size() + 5, self.states.regCaps["MaxSgpr"]) |
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"+5" should not be required for all kernels.
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That's right, this is meant to be a temporary fix to unblock perf teams. A debt ticket will be issued to more accurately collect the high-water mark. Any suggestions or insight is appreciated.
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Closing the pull request in this repo. Please refer to the migrated pull request for updates. |
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In regards to LWPTENSILE-1696 This includes 2 changes: - Unrestricted the temp sgprs needed for gsu from being contiguous, avoiding overflow for certain kernels - Account for additional temp sgprs that will be required for code gen, up to physical limits --- 🔁 Imported from [ROCm/hipBLASLt#2184](ROCm/hipBLASLt#2184) 🧑💻 Originally authored by @mahmoodw --------- Co-authored-by: mahmoodw <wmahmood@amd.com> Co-authored-by: mahmoodw <44450175+mahmoodw@users.noreply.github.com>
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In regards to LWPTENSILE-1696 This includes 2 changes: - Unrestricted the temp sgprs needed for gsu from being contiguous, avoiding overflow for certain kernels - Account for additional temp sgprs that will be required for code gen, up to physical limits --- 🔁 Imported from [ROCm/hipBLASLt#2184](ROCm/hipBLASLt#2184) 🧑💻 Originally authored by @mahmoodw --------- Co-authored-by: mahmoodw <wmahmood@amd.com> Co-authored-by: mahmoodw <44450175+mahmoodw@users.noreply.github.com>
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This includes 2 changes: - Unrestricted the temp sgprs needed for gsu from being contiguous, avoiding overflow for certain kernels - Account for additional temp sgprs that will be required for code gen, up to physical limits --- 🔁 Imported from [ROCm/hipBLASLt#2184](ROCm/hipBLASLt#2184) 🧑💻 Originally authored by @mahmoodw --------- Co-authored-by: assistant-librarian[bot] <210906412+assistant-librarian[bot]@users.noreply.github.com> Co-authored-by: mahmoodw <wmahmood@amd.com>
AlexBrownAMD
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This includes 2 changes: - Unrestricted the temp sgprs needed for gsu from being contiguous, avoiding overflow for certain kernels - Account for additional temp sgprs that will be required for code gen, up to physical limits --- 🔁 Imported from [ROCm/hipBLASLt#2184](ROCm/hipBLASLt#2184) 🧑💻 Originally authored by @mahmoodw --------- Co-authored-by: assistant-librarian[bot] <210906412+assistant-librarian[bot]@users.noreply.github.com> Co-authored-by: mahmoodw <wmahmood@amd.com>
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Jul 15, 2025
This includes 2 changes: - Unrestricted the temp sgprs needed for gsu from being contiguous, avoiding overflow for certain kernels - Account for additional temp sgprs that will be required for code gen, up to physical limits --- 🔁 Imported from [ROCm/hipBLASLt#2184](ROCm/hipBLASLt#2184) 🧑💻 Originally authored by @mahmoodw --------- Co-authored-by: assistant-librarian[bot] <210906412+assistant-librarian[bot]@users.noreply.github.com> Co-authored-by: mahmoodw <wmahmood@amd.com>
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In regards to LWPTENSILE-1696
This includes 2 changes: