NetFPGA SUME Design Flow

#NetFPGA SUME Design Flow

The NetFPGA SUME reference projects are based on the Xilinx Vivado tool chain. The projects are all modular, meaning that they are built from basic components that allow users to easily change, upgrade or remove parts of their design.

IP Cores

Each stand alone module within the projects is referred to as a core or an IP (Intellectual property) block. Every core is built from a set of HDL files and script files that generate the core as an IP entity that Vivado can work with.

The NetFPGA SUME design opts for a tcl-based design flow. This means that using the Vivado GUI to create a project is not a must but an option. It allows people who have no knowledge in hardware design to easily compile and run existing projects, and people who want to rapidly prototype new devices to easily do so without high familiarity with Vivado's GUI.

Each IP core is composed of two parts: one or more HDL files (usually verilog), which define its function - like any standard HDL module, and a tcl file which wraps the code into an IP. For most new IP designs, a user is require to add or change in this file only the name of the vhdl or verilog files being used.

Project Generation

The top hierarchy of projects is being defined by a simple verilog wrapper. Below this wrapper many modules (typically IP cores) exist. A single tcl script generates a Vivado project for each such reference project, synthesizes and implements it. The IP cores that are being used in the design need to be defined in this script.

As some IP cores require parameter definition, this is also done through the project's tcl script. Unfortunately, Vivado currently does not support parameter propagation into IPs created on the project level (but parameters can be propagated within IP cores).

We expect to extend this page as more users start to develop over the NetFPGA SUME platform