Contrib. Core: Large CAM

Large CAM core

Description

Basically, this cam is based on Xilinx CAM (xapp1151_param_cam.zip), which has scalability limitation. To ensure large size entries (e.g., 1024), multiple Xilinx CAMs are combined. To reduce fan-out on the priority encoder and input multiplexer, buffers is builtin.

Specification

• 1024x48
• Read Latency : 4 clock cycles (BRAM-based and SRL-based)
• Write Latency : 2 clock cycles (BRAM-based), 10 clock cycles (SRL-based)
  • On using SRL-based CAM, write consistency will be problem. so some write caches are introduced in mac_cam_lut.v to conceal the latency.

Simulation

You need to download XAPP1152 for CAM implementation in Xilinx website. Please find zip file of "xapp1151_param_cam.zip" in search engine at Xilinx website.

setting.sh

export SUME_FOLDER=${HOME}/NetFPGA-SUME-live
export XILINX_PATH=/opt/Xilinx/Vivado/2016.4
export NF_PROJECT_NAME=reference_switch_lcam
export PROJECTS=${SUME_FOLDER}/contrib-projects
export CONTRIB_PROJECTS=${SUME_FOLDER}/contrib-projects
export IP_FOLDER=${SUME_FOLDER}/lib/hw/std/cores
export CONSTRAINTS=${SUME_FOLDER}/lib/hw/std/constraints
export XILINX_IP_FOLDER=${SUME_FOLDER}/lib/hw/xilinx/cores
export NF_DESIGN_DIR=${SUME_FOLDER}/contrib-projects/${NF_PROJECT_NAME}
export NF_WORK_DIR=/tmp/${USER}
export PYTHONPATH=.:${SUME_FOLDER}/tools/scripts/:${NF_DESIGN_DIR}/lib/Python:${SUME_FOLDER}/tools/scripts/NFTest
export DRIVER_NAME=sume_riffa_v1_0_0
export DRIVER_FOLDER=${SUME_FOLDER}/lib/sw/std/driver/${DRIVER_NAME}
export APPS_FOLDER=${SUME_FOLDER}/lib/sw/std/apps/${DRIVER_NAME}

How to simulate the cores

$ source $SUME_FOLDER/tools/settings
$ cd $SUME_FOLDER/ && make
$ cp xapp1151_Param_CAM.zip $SUME_FOLDER/lib/hw/contrib/cores/lcam_output_port_lookup_v1_0_0 && make update
$ cd $SUME_FOLDER/lib/hw/contrib/cores/lcam_output_port_lookup_v1_0_0 && make
$ cd $SUME_FOLDER/tools/scripts/
$ ./nf_test.py sim --major learning --minor sw

Contact

Yuta Tokusashi (Keio Univ.)
[email protected]