Contrib. Core: Rate Limiter

Name

rate_limiter

Version

v1.0.0

Author

Noa Zilberman

Type

Contrib IP core (HW)

Location

lib/hw/contrib/cores/rate_limiter_v1_0_0/

Interface Types

AXI4-Stream

AXI-Lite

Busses

M_AXIS: Master AXI4-Stream bus, Variable width

S_AXIS: Slave AXI4-Stream bus, Variable width

S_AXI: Slave AXI4-Lite

Parameters

C_M_AXIS_DATA_WIDTH: Data width of the master AXI4-Stream data bus.

C_S_AXIS_DATA_WIDTH: Data width of the slave AXI4-Stream data bus.

C_M_AXIS_TUSER_WIDTH: Data width of the master TUSER bus.

C_S_AXIS_TUSER_WIDTH: Data width of the slave TUSER bus.

C_BASEADDR: Base address value of the core.

C_HIGHADDR: High address value of the core.

Register map

0x0 : ID - Block ID

0x4 : VERSION - Block Version

0x8 : RESET - Clear counters and reset registers

0xC : FLIP - Returns the negative value of a written register

0x10 : PKTIN - Total number of incoming packets

0x14: PKTOUT - Total number of outgoing packets

0x18: DEBUG - Debug register, returns the written value plus a preconfigured value

0x1C - RATE_BASE - Set the base length on a cycle, in clocks

0x20 - RATE_VALID - Set the number of valid clocks in a cycle

Description

This module provides constant bit rate limiting. Refer to delay_mb project for more information.