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drivers: spi: Initial support for GD32 spi #40416

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Merged
merged 4 commits into from
Mar 29, 2022
Merged

drivers: spi: Initial support for GD32 spi #40416

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9025ed9
dts: arm: introduce gd32 spi interface
cameled Nov 23, 2021
b0f28c8
drivers: spi: introduce gd32 spi driver
cameled Nov 23, 2021
b8feeec
boards: add gd35q16 flash to gd32f450i_eval and gd32vf103v_eval boards
cameled Jan 18, 2022
ed965a2
samples: spi_flash: add gd32f450i_eval and gd32vf103v_eval boards
cameled Jan 18, 2022
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9 changes: 9 additions & 0 deletions boards/arm/gd32f450i_eval/gd32f450i_eval-pinctrl.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -30,4 +30,13 @@
drive-open-drain;
};
};

spi5_default: spi5_default {
group1 {
pinmux = <SPI5_SCK_PG13>, <SPI5_MOSI_PG14>,
<SPI5_MISO_PG12>,
/* Use pinmux to pullup pg10 and pg11. */
<SPI5_IO2_PG10>, <SPI5_IO3_PG11>;
};
};
};
25 changes: 25 additions & 0 deletions boards/arm/gd32f450i_eval/gd32f450i_eval.dts
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Expand Up @@ -89,6 +89,14 @@
status = "okay";
};

&gpioi {
status = "okay";
};

&gpiog {
status = "okay";
};

&usart0 {
status = "okay";
current-speed = <115200>;
Expand Down Expand Up @@ -128,3 +136,20 @@
timeout = <5>;
};
};

&spi5 {
status = "okay";
pinctrl-0 = <&spi5_default>;
pinctrl-names = "default";
cs-gpios = <&gpioi 8 GPIO_ACTIVE_LOW>;

nor_flash: gd25q16@0 {
compatible ="jedec,spi-nor";
size = <0x1000000>;
label = "GD25Q16";
reg = <0>;
spi-max-frequency = <4000000>;
status = "okay";
jedec-id = [c8 40 15];
};
};
7 changes: 7 additions & 0 deletions boards/riscv/gd32vf103v_eval/gd32vf103v_eval-pinctrl.dtsi
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Expand Up @@ -23,4 +23,11 @@
pinmux = <TIMER0_CH0_PA8_OUT_NORMP>;
};
};

spi0_default: spi0_default {
group1 {
pinmux = <SPI0_SCK_PA5_OUT_NORMP>, <SPI0_MOSI_PA7_OUT_NORMP>,
<SPI0_MISO_PA6_OUT_NORMP>;
};
};
};
17 changes: 17 additions & 0 deletions boards/riscv/gd32vf103v_eval/gd32vf103v_eval.dts
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Expand Up @@ -120,3 +120,20 @@
pinctrl-names = "default";
};
};

&spi0 {
status = "okay";
pinctrl-0 = <&spi0_default>;
pinctrl-names = "default";
cs-gpios = <&gpioe 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;

nor_flash: gd25q16@0 {
compatible ="jedec,spi-nor";
size = <0x1000000>;
label = "GD25Q16";
reg = <0>;
spi-max-frequency = <4000000>;
status = "okay";
jedec-id = [c8 40 15];
};
};
1 change: 1 addition & 0 deletions drivers/spi/CMakeLists.txt
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Expand Up @@ -28,5 +28,6 @@ zephyr_library_sources_ifdef(CONFIG_SPI_PSOC6 spi_psoc6.c)
zephyr_library_sources_ifdef(CONFIG_SPI_NPCX_FIU spi_npcx_fiu.c)
zephyr_library_sources_ifdef(CONFIG_SPI_BITBANG spi_bitbang.c)
zephyr_library_sources_ifdef(CONFIG_SPI_XEC_QMSPI_LDMA spi_xec_qmspi_ldma.c)
zephyr_library_sources_ifdef(CONFIG_SPI_GD32 spi_gd32.c)

zephyr_library_sources_ifdef(CONFIG_USERSPACE spi_handlers.c)
2 changes: 2 additions & 0 deletions drivers/spi/Kconfig
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Expand Up @@ -99,4 +99,6 @@ source "drivers/spi/Kconfig.bitbang"

source "drivers/spi/Kconfig.xec_qmspi_ldma"

source "drivers/spi/Kconfig.gd32"

endif # SPI
12 changes: 12 additions & 0 deletions drivers/spi/Kconfig.gd32
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@@ -0,0 +1,12 @@
# Copyright (c) 2021 BrainCo Inc.
# SPDX-License-Identifier: Apache-2.0

# Workaround for not being able to have commas in macro arguments
DT_COMPAT_GD_GD32_SPI := gd,gd32-spi

config SPI_GD32
bool "Gigadevice GD32 SPI driver"
depends on (SOC_FAMILY_GD32 || SOC_SERIES_GD32VF103)
default $(dt_compat_enabled,$(DT_COMPAT_GD_GD32_SPI))
help
Enables Gigadevice GD32 SPI driver.
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