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[KV cache] Add an mxfp4 kv_cache_dtype - #64358

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amd-dlimpus:cursor/m31-mxfp4-kv-cache-dtype-a294
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amd-dlimpus wants to merge 4 commits into
vllm-project:mainfrom
amd-dlimpus:cursor/m31-mxfp4-kv-cache-dtype-a294

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@amd-dlimpus amd-dlimpus commented Oct 28, 2026 •

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Overview

Adds kv_cache_dtype="mxfp4" for a non-MLA KV cache: E2M1 data with one E8M0 scale per 32 elements (OCP MX), stored as uint8.

  • CacheDType gains "mxfp4", and STR_DTYPE_TO_TORCH_DTYPE maps it to torch.uint8.
  • KVQuantMode.MXFP4 = 17 (15 is MXFP4_DS_MLA in [ROCm][DSv4.1] MXFP4 compressed KV cache (mxfp4_ds_mla) on gfx950 #64120, and 16 is used by another open MXFP4 PR), returned by get_kv_quant_mode("mxfp4"), with an is_mxfp4 property. It is its own mode, not CUSTOM, so backends can key on it like NVFP4.
  • mxfp4_kv_cache_full_dim(head_size) gives the packed bytes per head: head_size / 2 + head_size / 32, which is 68 for 128. Unlike nvfp4_kv_cache_full_dim (72 for 128), there is no global scale.

Motivation

MiniMax-M3.1 on MI355X (gfx950) can decode from an MXFP4 KV and index cache using the native V_MFMA_SCALE_F32_*_F8F6F4 instructions, which take E8M0 per-32 scales. That's 204 B per token and layer, against 216 B for NVFP4. An accuracy check that rounds K, V and index-K to MXFP4 on today's FP8 path showed no significant loss against the NVFP4-KV baseline (paired exact McNemar, seed 42):

Bench NVFP4 KV MXFP4 KV (emulated) p
GSM8K (1319) 94.31% 94.31% 1.0
GPQA-Diamond (198) 80.30% 83.33% 0.39
RULER NIAH multikey-2 32k (50) 100% 100% 1.0

Stack

This is the bottom of a stack; the first consumer is the MiniMax-M3 MXFP4 page writer, which is stacked on #63232. Readers and the backend that selects this dtype follow in later PRs. Until then nothing selects "mxfp4".

Validation

tests/config/test_kv_cache_dtype.py::test_mxfp4_kv_cache_dtype covers the dtype name, CacheConfig, the torch dtype, the quant mode and its properties, and the 68-byte full dim. It passes on CPU.


Pull Request Checklist
  • I used vLLM's /pr-checklist skill. (Mandatory for agents, optional for humans).

  • AI assistance was used during the creation of this PR.

  • Design Fit: Minimizes impact on core components, reuses existing functionality, and justifies added complexity.

  • Testing and Validation: Validates the change and ensures any added tests are meaningful and reliable, with CI coverage or documented CI resource constraints and validation performed outside CI.

  • Code Quality and Style: Keeps code and comments clear and concise, and updates relevant documentation and examples.

  • Pull Request Contents: Includes a brief summary and relevant links, supports claims with evidence, explains root causes and implementation trade-offs, and follows the contributing guide.

Per-head MXFP4 KV: E2M1 data plus one E8M0 scale per 32 elements, stored
as uint8 (head_size/2 + head_size/32 bytes per head row, 68 for 128),
with its own KVQuantMode.MXFP4. Backends opt in through
supported_kv_cache_dtypes.

Signed-off-by: Limpus, David <dlimpus@amd.com>
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🚀

…de.MXFP4 = 16)

Move KVQuantMode.MXFP4 from 15 to 16, since 15 is MXFP4_DS_MLA in vllm-project#64120,
and make the cache.py, torch_utils.py and kv_cache_interface.py hunks
identical to c7f5944 in vllm-project#64198 so whichever PR lands second drops a
clean duplicate.

Signed-off-by: Limpus, David <dlimpus@amd.com>
…VQuantMode.MXFP4 = 16)"

This reverts commit 762bcf8.

Signed-off-by: Limpus, David <dlimpus@amd.com>
15 is MXFP4_DS_MLA in vllm-project#64120 and 16 is MXFP4 in vllm-project#64198.

Signed-off-by: Limpus, David <dlimpus@amd.com>

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