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[ROCm][Perf] Split-K BF16x3 router GEMM for decode batches - #62614
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The ROCm BF16x3 router tier (fp32 gate weights, e.g. MiniMax-M2/M3) only served batches of 2048+ tokens; decode batches between the gfx950 fp32 low-M kernel (M<=32) and 2048 fell back to F.linear on the fp32 pipe. Add a split-K Triton kernel that keeps the three bf16 weight terms in separate accumulators, then sums the K partitions in a fixed order, and route every batch above the fp32 low-M kernel and below 2048 tokens to it. On MI355X it is 1.6-2.1x faster than F.linear and 1.1-1.8x faster than the stacked hipBLASLt GEMM over that range at the MiniMax-M2/M3 router shapes, and more accurate than F.linear (rel. L2 vs fp64 1.1e-7 to 2.4e-7, vs 2e-7 to 1.4e-6). Co-Authored-By: Claude <noreply@anthropic.com> Signed-off-by: jiacao-amd <jiahui.cao@amd.com>
This was referenced Oct 24, 2026
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Closing: on MiniMax-M3.1-Flash AgenticX (c16, TP4) decode steps rarely exceed 32 rows, so the split-K path is not reached often enough to show up end to end. |
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Purpose
The ROCm BF16x3 router tier (
bf16x3_router_gemm_rocm, fp32 gate weights as in MiniMax-M2/M3) only serves batches of 2048+ tokens. Decode batches above the gfx950 fp32 low-M kernel (M ≤ 32) and below 2048 fall back toF.linear(x.float(), w)on the fp32 pipe, which is both slower and less accurate.This PR adds a split-K Triton kernel for that range:
BLOCK_M × K/SPLIT_Kslice of the bf16 activations and the matching slices of the three bf16 weight terms, and accumulates the three terms in separate fp32 accumulators (small terms are summed among themselves before meeting the large one).SPLIT_Kis chosen so the grid stays within 768 programs while each split keeps ≥192 of K (within 3% of the best split on average, 16% worst case, over M ∈ [64, 2047] and six router shapes).Dispatch (
rocm_bf16x3_router_gemm_dispatch): M ≤ 32 → existing fp32 low-M kernel (still fastest there); 32 < M < 2048 → split-K; M ≥ 2048 → existing stacked hipBLASLt GEMM. Arbitrary M/N/K are supported via masks (N=17/384, K=1000/2880 and padded activation rows are tested).Microbenchmark (MI355X, µs per call, CUDA graph over 57 distinct weights)
Accuracy (rel. L2 vs fp64): split-K 1.1e-7 – 2.4e-7, F.linear 2e-7 – 1.4e-6.
E2E (MI355X, MiniMax-M3-MXFP4, TP4, EAGLE3 K=3)
vLLM nightly
8e2beaa3(AITER v0.1.26) plus #61889, which that nightly needs to start MiniMax-M3; the baseline is the same image without this PR. AgenticX: InferenceX recipeminimaxm3/vllm/mi355x-fp4-mtp/agentic.yaml, 3600 s per point, one run each (run-to-run noise is about ±3%). Cells are baseline → this PR.AgenticX (selected points; also measured: C1, C4, C8, C15, C20)
The new kernel serves decode batches above 32 tokens (more than 8 running requests with K=3): about 29% of the time at C24 and 63% at C32. At C15 and below the dispatch is unchanged.
8k/1k C24 (240 requests, every decode batch is in the split-K range; measured on nightly
1b2a666plus ROCm/aiter#6336, 2 interleaved rounds vs a same-round baseline):Accuracy (GSM8K), InferenceX
gsm8k.yaml, 5-shot, all 1,319 questions, real EAGLE3 acceptance, thinking on:Standard error ±0.53%.
The kernel is also more accurate than the
F.linearfp32 path it replaces (relative L2 vs fp64 above), and a real-acceptance greedy smoke (24 concurrent ≥8k-token prompts + 4 short) generated text identical to the baseline (24/24, 4/4).Test Plan
pytest tests/kernels/test_bf16x3_router_gemm_rocm.py tests/kernels/test_gate_linear_rocm_dispatch.pyon gfx950 — 220 passed. New cases: fp64 reference across M ∈ {1, 33, 96, 257, 1000, 2047, …}, non-power-of-two experts and ragged K, strided activations, determinism, config bounds, more-accurate-than-F.linear and expert-selection checks at decode M, and dispatch routing by M.Draft: E2E covers MiniMax-M3 only; MiniMax-M2 / HunYuan-V3 E2E not yet measured.
🤖 Generated with Claude Code