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[Perf][Kernel] Qwen4Exp QSA: SM90 native sparse prefill kernel - #59010

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@charon14 charon14 commented Sep 28, 2026 •

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Purpose

On Hopper, QSA sparse prefill attention for Qwen3.8-Flash-Next runs _qsa_sparse_paged_gqa_splitk_kernel with the (32, 1, 1) prefill config. Every query attends to its own 2048 selected tokens, and one KV group has only 12 (TP1/TP2), 6 (TP4) or 3 (TP8) query heads, so the Triton kernel is limited to one warp and mma.sync with M padded to 16. On H20, ncu shows it is not memory bound: DRAM reads are under 1% of peak, and L2 hit rate is 99% because one request's K/V for one layer fits in L2. The tensor pipe is 58% busy with math_pipe_throttle as the top stall, which is 28% of BF16 peak. Retuning BLOCK_N / warps / stages does not help, and a transposed Triton variant that could use wgmma needs 142 KB of shared memory per program and runs 2x slower.

This PR adds a CUDA/CuTe kernel for that path with the same semantics as the one-split Triton kernel. It is used only on SM90 with a BF16 KV cache and prefill-config launches above 2048 (row, KV head) programs. Everything else keeps the Triton kernel:

  • Both GEMMs are transposed so the selected keys take the wgmma M dimension: S^T[64x16] = K·Q^T and O^T[256x16] += V^T·P^T, both m64n16k16. The online softmax runs per head column, with one cross-warp max exchange per 64-key tile.
  • The first 64 threads resolve each selected token to a 32-bit offset (block table lookup included). Each warp then gathers whole 512-byte K or V rows with 16-byte cp.async directly into the swizzled wgmma layouts.
  • K and V are single-buffered with staged prefetch. Each buffer is refilled only after a CTA-wide barrier that follows every warp's wgmma on it. Token metadata is resolved two tiles ahead, overlapping QK. Shared memory is 75 KB and registers are 156 with no spills, so 3 CTAs fit per SM.
  • The epilogue fuses the output gate with the same rounding as the Triton kernel (#55309): the attention output is rounded to BF16, then multiplied by sigmoid(gate) in FP32.

The kernel lives in csrc/libtorch_stable/attention/qsa/qsa_sm90.cu and is built only for 9.0a. The op _C::qsa_sparse_prefill_sm90 is registered in that file, so it exists only when it was built. qsa_sparse_paged_attention dispatches to it after its argument checks. Unsupported layouts (K/V rows not 16-byte aligned, a cache span over 64 GiB, group > 16, head_dim != 256) log once and fall back to Triton. VLLM_QSA_SM90_NATIVE=0 disables the kernel.

Not a duplicate. I searched open and closed PRs for qsa sm90, qsa hopper, qsa h20, qsa prefill kernel, qsa native, qsa wgmma, qsa cuda, sparse gqa and Qwen4Exp sparse attention kernel, and found no SM90 kernel for this path:

  • #56240 (FlashInfer PrimTS) targets SM100/SM103 only. If it lands, this kernel could become an sm90 value of its VLLM_QSA_ATTENTION_BACKEND.
  • #57273 retuned only the SM90 decode region; the prefill region, which this PR replaces, stayed (32, 1, 1).
  • FP8 KV caches (#55557, #54846) stay on Triton.
  • #53909 adds standalone Triton ops.
  • #55430 (cross-query tile union) was closed. On H20, adjacent queries share only about 71% of their selected keys, so a union costs 1.6-2.5x more MMA work on a compute-bound kernel.

Test Plan

All runs were on 8x H20 (96 GB), CUDA 13.3, torch 2.13.0, on this branch built with TORCH_CUDA_ARCH_LIST=9.0a. Native vs Triton is toggled with VLLM_QSA_SM90_NATIVE=1/0.

# Unit tests: native kernel vs the one-split Triton kernel and the dense reference
# (group sizes 3/6/12/16, ragged rows, -1 holes, empty rows, invalid requests, short
# contexts, page sizes 64/784/1568/1600, padded hybrid block strides), opcheck, dispatch.
pytest tests/models/qwen4_exp/test_qsa_reference.py

# Kernel benchmark, per-rank head splits of TP1/TP2/TP4/TP8
python benchmarks/kernels/benchmark_qsa_sm90_prefill.py

# compute-sanitizer on small shapes (ragged/holes/invalid/empty rows, page 64, group 3, padded stride)
compute-sanitizer --tool {memcheck,racecheck,synccheck,initcheck} python <script calling ops.qsa_sparse_prefill_sm90>

# Accuracy: the tests/evals/qwen4_exp EvalScope task (run_evalscope from test_accuracy.py,
# GSM8K + AIME25, config Qwen3.8-Flash-Next-FP8.yaml: TP4, thinking, same generation config)
# against one server per arm (VLLM_QSA_SM90_NATIVE=1/0); AIME25 repeated with seeds 1237/1238.
# Equivalent to this, with the env added to the config:
pytest -s -v tests/evals/qwen4_exp/test_accuracy.py --config-list-file=configs/models-h200.txt

# Prefill-heavy serving A/B (TP4, both arms on identical servers, alternating runs)
vllm serve Qwen/Qwen3.8-Flash-Next-FP8 --tensor-parallel-size 4
vllm bench serve --backend vllm --dataset-name random --random-input-len 16000 \
    --random-output-len 8 --ignore-eos --max-concurrency 16 --num-prompts 128 --seed {0,2}

Test Result

Unit tests: test_qsa_reference.py passes, 83 tests (73 existing + 10 new). The native kernel's max abs difference from the Triton kernel is at most 2e-3 on production-shaped inputs, and at most one BF16 ulp of the gated output elsewhere.

compute-sanitizer: memcheck 0 errors, racecheck 0 hazards, synccheck 0 errors, initcheck 0 errors.

Kernel (H20), benchmark_qsa_sm90_prefill.py, median ms through qsa_sparse_paged_attention:

split (Q/KV heads per rank) rows context Triton native speedup
TP1 (24/2) 2048 21000 2.652 1.693 1.57x
TP1 (24/2) 8192 21000 10.177 6.653 1.53x
TP1 (24/2) 16384 65536 21.943 14.780 1.48x
TP2 (12/1) 8192 65536 5.603 3.799 1.47x
TP4 (6/1) 8192 21000 4.518 3.306 1.37x
TP4 (6/1) 16384 65536 9.436 7.173 1.32x
TP8 (3/1) 16384 21000 8.969 6.527 1.37x
All shapes
split   rows  context  triton ms  native ms  speedup  max diff
  tp1   2048     4096      2.614      1.690    1.55x   9.8e-04
  tp1   2048    21000      2.652      1.693    1.57x   9.8e-04
  tp1   2048    65536      2.923      1.924    1.52x   9.8e-04
  tp1   4096     4096      3.958      2.615    1.51x   7.8e-03
  tp1   4096    21000      5.146      3.323    1.55x   9.8e-04
  tp1   4096    65536      5.626      3.783    1.49x   9.8e-04
  tp1   8192    21000     10.177      6.653    1.53x   9.8e-04
  tp1   8192    65536     11.101      7.547    1.47x   9.8e-04
  tp1  16384    21000     20.187     13.169    1.53x   9.8e-04
  tp1  16384    65536     21.943     14.780    1.48x   9.8e-04
  tp2   4096     4096      1.998      1.305    1.53x   3.9e-03
  tp2   4096    21000      2.599      1.682    1.54x   9.8e-04
  tp2   4096    65536      2.893      1.896    1.53x   9.8e-04
  tp2   8192    21000      5.143      3.349    1.54x   9.8e-04
  tp2   8192    65536      5.603      3.799    1.47x   9.8e-04
  tp2  16384    21000     10.128      6.652    1.52x   9.8e-04
  tp2  16384    65536     11.025      7.417    1.49x   9.8e-04
  tp4   4096     4096      1.759      1.285    1.37x   3.9e-03
  tp4   4096    21000      2.311      1.658    1.39x   9.8e-04
  tp4   4096    65536      2.481      1.839    1.35x   9.8e-04
  tp4   8192    21000      4.518      3.306    1.37x   9.8e-04
  tp4   8192    65536      4.795      3.612    1.33x   9.8e-04
  tp4  16384    21000      8.901      6.566    1.36x   9.8e-04
  tp4  16384    65536      9.436      7.173    1.32x   9.8e-04
  tp8   4096     4096      1.771      1.273    1.39x   3.9e-03
  tp8   4096    21000      2.326      1.650    1.41x   9.8e-04
  tp8   4096    65536      2.507      1.805    1.39x   9.8e-04
  tp8   8192    21000      4.540      3.288    1.38x   9.8e-04
  tp8   8192    65536      4.848      3.602    1.35x   9.8e-04
  tp8  16384    21000      8.969      6.527    1.37x   9.8e-04
  tp8  16384    65536      9.532      7.082    1.35x   9.8e-04

Every benchmarked shape above the dispatch threshold is faster: 1.47-1.57x at TP1/TP2 (group 12) and 1.32-1.41x at TP4/TP8 (group 6/3, where N=16 padding costs more). The production-sized TP1 chunk (15,094 rows, full 2048-token selections) goes from 18.44 ms to 11.94 ms (1.54x). Replays of real indexer selections dumped from a server go from 18.02/18.08 ms to 11.87/11.85 ms (1.52x/1.53x). The fused gate epilogue costs 2.2-2.9% of kernel time.

Serving (TP4, H20), 16k-token prompts, 8 output tokens, concurrency 16, 128 prompts, two seeds:

Triton native change
total token throughput (tok/s) 15,083 / 15,083 15,416 / 15,413 +2.2%
mean TTFT (s) 12.81 / 12.81 12.53 / 12.53 -2.2%
median TTFT (s) 13.26 / 13.25 12.99 / 12.99 -2.0%

In our TP1 DP4/EP4 multimodal deployment on an older base, QSA per call went from 17.5 ms to 11.4 ms in nsys, and end-to-end throughput rose 3.9%.

Accuracy, tests/evals/qwen4_exp, Qwen3.8-Flash-Next-FP8, TP4, same seeds and generation config:

dataset threshold (tolerance) Triton native
GSM8K (seed 1236) 0.98 (0.02) 0.9765 0.9780
AIME25, seeds 1236 / 1237 / 1238 0.90 (0.05) 0.933 / 0.900 / 0.933 (mean 0.922) 0.900 / 0.967 / 0.900 (mean 0.922)

Both arms pass every run, and AIME25 misses come from the same hard problems in both arms: #13 in all six runs, and #14 and #29 in both arms. The one extra native miss at seed 1236 (#29) hit the 32k max_tokens limit before a final answer.

GSM8K and AIME25 prompts are short, so most of their prefill launches stay under the dispatch threshold. To exercise the native path on long contexts, I also compared both arms on 4 long prompts (7.8k-31k tokens, greedy, 128 tokens). Both servers scored the same token sequence (prompt + Triton's greedy continuation) with prompt_logprobs:

prompt tokens argmax agreement differing positions: Triton top1-top2 margin mean / max abs logprob diff
7,836 128/128 - 0.020 / 0.23
18,546 128/128 - 0.016 / 0.15
7,960 115/117 0.00, 0.25 0.031 / 0.29
31,349 124/128 0.125 x4 0.035 / 0.26

Every disagreement is at a near tie. For scale, repeating the same greedy request on the same server, where the repeat hits the prefix cache, changes the output on 3 of 4 prompts for Triton and 2 of 4 for native.

Notes for reviewers

  • Tested on H20 only. H100/H200 have about 4x the tensor throughput, so the balance may shift toward loads. I can restrict the dispatch to measured devices or default it off if preferred.
  • AI assistance: this PR was developed with AI assistance (Claude, via Cursor), including the kernel, tests and benchmarks. The commit carries a Co-authored-by trailer. I have reviewed every changed line.

Essential Elements of an Effective PR Description Checklist
  • The purpose of the PR, such as "Fix some issue (link existing issues this PR will resolve)".
  • The test plan, such as providing test command.
  • The test results, such as pasting the results comparison before and after, or e2e results
  • (Optional) The necessary documentation update, such as updating supported_models.md and examples for a new model.

Large QSA sparse prefill launches over BF16 KV caches on SM90 run a
CUDA/CuTe kernel instead of the one-split Triton kernel. Both GEMMs are
transposed so the selected keys take the wgmma M dimension; the output
gate is fused into the epilogue with the Triton kernel's BF16 rounding.
FP8 caches, decode-config launches and other devices keep the Triton
path; VLLM_QSA_SM90_NATIVE=0 disables the native kernel.

Co-authored-by: Claude
Signed-off-by: Milo <7bit2333@gmail.com>
@mergify mergify Bot added ci/build performance Performance-related issues qwen Related to Qwen models labels Sep 28, 2026
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@gau-nernst

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Is the speedup mainly from swapAB MMA? Have you tried doing swapAB for the triton kernel?

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mergify Bot commented Oct 30, 2026

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This pull request has merge conflicts that must be resolved before it can be
merged. Please rebase the PR, @charon14.

https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/working-with-forks/syncing-a-fork

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