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[Qwen3.8-Flash-Next] Support FP8 indexer cache for QSA - #54890

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ZJY0516 merged 11 commits into
vllm-project:mainfrom
gau-nernst:qwen38next-fp8-indexer
Sep 7, 2026
Merged

ZJY0516 merged 11 commits into
vllm-project:mainfrom
gau-nernst:qwen38next-fp8-indexer

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@gau-nernst gau-nernst commented Sep 2, 2026

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Purpose

This PR adds FP8 support for QSA indexer. This implementation doesn't contain any scaling.

Microbenchmarks

All measurements are done on GB300

Decode

bs ctx dql=1 bf16 -> fp8 dql=4 bf16 -> fp8
1 8k 3.9 -> 3.7 (1.0x) 4.0 -> 4.0 (1.0x)
1 64k 4.8 -> 4.3 (1.1x) 5.0 -> 4.4 (1.1x)
4 8k 4.3 -> 4.0 (1.1x) 4.4 -> 4.3 (1.0x)
4 64k 7.6 -> 6.1 (1.3x) 8.2 -> 6.5 (1.3x)
16 8k 5.8 -> 4.8 (1.2x) 6.0 -> 5.1 (1.2x)
16 64k 16.9 -> 11.1 (1.5x) 18.4 -> 12.9 (1.4x)

Prefill

ctx rows bf16 fp8 speedup
8k 2048 27.7 15.8 1.7x
8k 8192 (chunk) 43.2 31.3 1.4x
32k 2048 42.2 31.3 1.4x
32k 16384 (chunk) 272.9 187.2 1.5x
128k 2048 146.5 98.8 1.5x
128k 4096 (chunk) 260.4 186.6 1.4x

Generally the speedup is not linear, hinting Triton's inefficiencies. Future PRs can address FP8 performance (I have WIP branches for CuteDSL decode and Triton TMA prefill)

E2E performance

TP4 GB300, 8k-1k

concurrency TTFT P50 bf16 (s) TTFT P50 fp8 (s) TPOT P50 bf16 (ms) TPOT P50 fp8 (ms)
1 0.16 0.16 4.58 4.58
4 0.34 0.42 6.36 6.26
16 0.53 0.59 10.22 10.20
64 0.61 0.61 19.88 19.85

The result is mostly noise because indexer contributes little to e2e timing at short context + we are using BF16 ckpt. TTFT at c=4 is likely an anomaly.

Test Plan

Unit tests

Updated in this PR

E2E tests

BF16 checkpoint, TP4 on GB300. Both with think=false (fast eval)

Branch GSM8K (5-shot, n=2638) LongBench-v2 (n=503)
bf16 (main) 0.9682 flex / 0.9689 strict 0.4871
fp8 indexer (this PR) 0.9678 / 0.9685 0.5050

FP8 is better. Likely within noise

Test Result


Essential Elements of an Effective PR Description Checklist
  • The purpose of the PR, such as "Fix some issue (link existing issues this PR will resolve)".
  • The test plan, such as providing test command.
  • The test results, such as pasting the results comparison before and after, or e2e results
  • (Optional) The necessary documentation update, such as updating supported_models.md and examples for a new model.

@mergify mergify Bot added the qwen Related to Qwen models label Sep 2, 2026
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mergify Bot commented Sep 4, 2026

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This pull request has merge conflicts that must be resolved before it can be
merged. Please rebase the PR, @gau-nernst.

https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/working-with-forks/syncing-a-fork

@mergify mergify Bot added the needs-rebase label Sep 4, 2026
@gau-nernst
gau-nernst force-pushed the qwen38next-fp8-indexer branch from 4091b23 to 493d8f4 Compare September 4, 2026 11:50
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Review Change Stack

No actionable comments were generated in the recent review. 🎉

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Run ID: e98459b1-5078-4aa8-9958-cad683ab1c63

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Reviewing files that changed from the base of the PR and between c2bf1a6 and 6fceb71.

📒 Files selected for processing (3)
  • tests/models/qwen4_exp/test_qsa_pre_indexer.py
  • tests/models/qwen4_exp/test_qsa_reference.py
  • vllm/models/qwen4_exp/nvidia/ops/qsa_indexer.py

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📝 Summary

Summary by CodeRabbit

  • New Features
    • Added optional FP8 (E4M3) support for Qwen4Exp QSA compressed KV caches, alongside BF16.
    • QSA indexer operations now automatically use the configured cache precision.
  • Bug Fixes
    • Added validation to detect mismatched query and cache data types and provide clearer error messages.
  • Tests
    • Expanded correctness coverage for both BF16 and FP8 cache configurations.

Walkthrough

The QSA indexer now supports BF16 and FP8 E4M3 compressed caches. Dtype resolution, cache validation, kernel launch parameters, query handling, and correctness tests cover both formats.

Changes

QSA FP8 indexer support

Layer / File(s) Summary
Dtype resolution and cache contracts
vllm/models/qwen4_exp/common/qsa_cache.py, vllm/models/qwen4_exp/nvidia/indexer_qsa.py
The backend advertises FP8 cache dtypes. Cache binding validates the configured dtype. The indexer applies BF16 or FP8 E4M3 to query and compressed-key storage.
Dtype-aware QSA kernel execution
vllm/models/qwen4_exp/nvidia/ops/qsa_indexer.py
Decode and prefill kernels require matching query and cache dtypes. FP8 caches select dedicated warp, tile, and stage parameters.
BF16 and FP8 correctness coverage
tests/models/qwen4_exp/test_qsa_pre_indexer.py, tests/models/qwen4_exp/test_qsa_reference.py
Tests cover fused, decode, and prefill paths with BF16 and FP8. FP8 comparisons use dtype-specific ULP or tolerance rules.

Estimated code review effort: 3 (Moderate) | ~25 minutes

Merge Risk: 🔵 Low · up to 6fceb

FP8 QSA cache support is covered across dtype handling and selection paths, but the FP8 correctness check can still accept matching NaN outputs, potentially masking a numerical regression. This is a bounded test-coverage risk to address before relying on the new mode broadly.

Sequence Diagram(s)

sequenceDiagram
  participant QSAIndexer
  participant QSAStateCache
  participant QSAKernels
  QSAIndexer->>QSAStateCache: allocate compressed key cache with indexer dtype
  QSAIndexer->>QSAKernels: submit matching query and cache dtypes
  QSAKernels->>QSAKernels: select dtype-specific launch parameters
  QSAKernels-->>QSAIndexer: return selection results
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🚥 Pre-merge checks | ✅ 4 | ❌ 1

❌ Failed checks (1 warning)

Check name Status Explanation Resolution
Docstring Coverage ⚠️ Warning Docstring coverage is 33.33% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 18 functions across 5 files. Write docstrings for the functions missing them to satisfy the coverage threshold.
✅ Passed checks (4 passed)
Check name Status Explanation
Title check ✅ Passed The title clearly and concisely describes the main change: adding FP8 indexer-cache support for QSA.
Description check ✅ Passed The description is directly related to the changeset and includes the purpose, benchmarks, E2E results, and test information.
Linked Issues check ✅ Passed Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check ✅ Passed Check skipped because no linked issues were found for this pull request.
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Add an opt-in fp8_e4m3 path for the QSA indexer/selector, following the
MiniMax M3 pattern: the normed indexer Q and the compressed K cache share
a plain e4m3 dtype with no scale column (values are GemmaRMSNormed before
caching), and the logits kernels dot fp8 x fp8 directly. Selected via
`attention_config.indexer_kv_dtype` ("bf16" default, "fp8"/"fp8_e4m3"
opt-in, SM90/SM100-family only since Triton cannot multiply fp8e4nv on
SM120/SM121).

The logits Triton kernels themselves are unchanged: tl.dot follows the
pointer dtypes (native fp8 tcgen05 at prefill tile sizes, auto-upcast to
fp16 mma.sync at decode tile sizes on SM100) and the store epilogues
convert implicitly.

Microbenchmark on GB300 (SM103a), indexer logits kernels: decode ~1.9x
bf16 at large batch x context (memory-bound, ~6.9 TB/s), prefill ~1.2x
bf16. See workspace/qwen38-fp8-indexer/RESULTS.md.

Tests: test_qsa_reference.py and test_qsa_pre_indexer.py parametrized
with the fp8 dtype (72 passed). E2E on Qwen/Qwen3.8-Flash-Next: bf16 and
fp8 both pass needle QA at 4.9k/19.5k/39k ctx with matching reasoning
traces and mean prompt logprob deltas <= 0.008.

Co-authored-by: Kimi Code CLI <noreply@moonshot.cn>
Signed-off-by: Thien Tran <gau.nernst@yahoo.com>

Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
- Compare fused vs unfused fp8 outputs in uint8 code space (one e4m3
  ulp = one code step; sign-magnitude makes code order match value
  order), with an absolute-tolerance fallback for the denormal range
  where intermediates differ absolutely due to pooling/norm cancellation
- Trim comments; drop unverified claims about SM120-family Triton fp8
  support (the gate stays conservative: SM90/SM100-family only)

Co-authored-by: Kimi Code CLI <noreply@moonshot.cn>
Signed-off-by: Thien Tran <gau.nernst@yahoo.com>

Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
fp8e4nv dots work on SM120 too; the capability check was unnecessary.

Co-authored-by: Kimi Code CLI <noreply@moonshot.cn>
Signed-off-by: Thien Tran <gau.nernst@yahoo.com>

Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
fp8 halves the K-tile bytes, shifting the memory-bound optimum of the
indexer logits kernels (measured on GB300/SM103a, configs swept on
production shapes):

- decode: num_warps 2 -> 1 for fp8 (up to 1.21x at dql=4 long-context,
  neutral at dql=1); bf16 keeps 2 (fp8's choice slightly regresses it)
- prefill: TILE_R 64 -> 32 and STAGES 2 -> 3 for fp8 (1.04-1.15x across
  8k-128k); bf16 keeps its constants

End-to-end select (logits+topk) fp8 vs bf16 on GB300: decode 1.82x
(dql=1) / 1.59x (dql=4) at 128k ctx B=512; prefill 1.12-1.15x.

Co-authored-by: Kimi Code CLI <noreply@moonshot.cn>
Signed-off-by: Thien Tran <gau.nernst@yahoo.com>

Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
…ect#54915 kernel

The clipped-logits prefill kernel from vllm-project#54915 shifts the fp8 optimum:
TILE_R=32 with num_warps=8/STAGES=2 beats the previously tuned
warps=4/STAGES=3 by 1.13-1.14x at 32k-128k (GB300/SM103a, in-tree kernel
launched with production-shaped clipped logits). bf16 constants unchanged.

Co-authored-by: Kimi Code CLI <noreply@moonshot.cn>
Signed-off-by: Thien Tran <gau.nernst@yahoo.com>

Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
- Drop the fp8_e4m3 spelling from the QSA indexer dtype branch: the
  IndexerKVDType literal never accepts it, so the branch was dead
- De-BF16 the QSA side-cache docstrings now that the dtype is configurable
- Add a spec->bind test for the compressed cache in both dtypes

Co-authored-by: Kimi Code CLI <noreply@moonshot.cn>
Signed-off-by: Thien Tran <gau.nernst@yahoo.com>

Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
The test added in vllm-project#55272 drives the unfused path with a SimpleNamespace
indexer; it needs the dtype attribute that path reads.

Co-authored-by: Kimi Code CLI <noreply@moonshot.cn>
Signed-off-by: Thien Tran <gau.nernst@yahoo.com>

Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
@gau-nernst
gau-nernst force-pushed the qwen38next-fp8-indexer branch from dc7d2b8 to de5a7cf Compare September 7, 2026 05:22
The bind guard fails loudly at engine init, so a unit test for the wiring
is not worth the lines.

Co-authored-by: Kimi Code CLI <noreply@moonshot.cn>
Signed-off-by: Thien Tran <gau.nernst@yahoo.com>

Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
… comments

Co-authored-by: Kimi Code CLI <noreply@moonshot.cn>
Signed-off-by: Thien Tran <gau.nernst@yahoo.com>

Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
Co-authored-by: Kimi Code CLI <noreply@moonshot.cn>
Signed-off-by: Thien Tran <gau.nernst@yahoo.com>

Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
@gau-nernst
gau-nernst marked this pull request as ready for review September 7, 2026 07:01

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/ci run

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✅ Triggered Buildkite CI #87503 for commit c2bf1a6d173c.

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Actionable comments posted: 1

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only still-valid issues, skip the rest with a brief reason, keep changes
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Inline comments:
In `@tests/models/qwen4_exp/test_qsa_pre_indexer.py`:
- Line 61: Update assert_fp8_within_one_ulp to reject non-finite values before
calculating or asserting FP8 code differences, ensuring identical
torch.float8_e4m3fn NaN codes cannot pass the one-ULP check.

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  • tests/models/qwen4_exp/test_qsa_pre_indexer.py
  • tests/models/qwen4_exp/test_qsa_reference.py
  • vllm/models/qwen4_exp/common/qsa_cache.py
  • vllm/models/qwen4_exp/nvidia/indexer_qsa.py
  • vllm/models/qwen4_exp/nvidia/ops/qsa_indexer.py

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Comment thread tests/models/qwen4_exp/test_qsa_pre_indexer.py Outdated
@ZJY0516
ZJY0516 enabled auto-merge (squash) September 7, 2026 07:12
@github-actions github-actions Bot added the ready ONLY add when PR is ready to merge/full CI is needed label Sep 7, 2026
Comment thread tests/models/qwen4_exp/test_qsa_pre_indexer.py
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
auto-merge was automatically disabled September 7, 2026 08:57

Head branch was pushed to by a user without write access

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/ci run

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✅ Triggered Buildkite CI #87519 for commit 6fceb7136580.

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ZJY0516 enabled auto-merge (squash) September 7, 2026 11:20
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ZJY0516 merged commit 94e26dd into vllm-project:main Sep 7, 2026
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@gau-nernst
gau-nernst deleted the qwen38next-fp8-indexer branch September 9, 2026 03:47
ItsRoy69 pushed a commit to ItsRoy69/vllm that referenced this pull request Sep 10, 2026
…54890)

Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
Signed-off-by: Jyotirmoy Roy <jyotirmoyroy649@gmail.com>
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