[Qwen3.8-Flash-Next] Support FP8 indexer cache for QSA - #54890
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WalkthroughThe QSA indexer now supports BF16 and FP8 E4M3 compressed caches. Dtype resolution, cache validation, kernel launch parameters, query handling, and correctness tests cover both formats. ChangesQSA FP8 indexer support
Estimated code review effort: 3 (Moderate) | ~25 minutes Merge Risk: 🔵 Low · up to FP8 QSA cache support is covered across dtype handling and selection paths, but the FP8 correctness check can still accept matching NaN outputs, potentially masking a numerical regression. This is a bounded test-coverage risk to address before relying on the new mode broadly. Sequence Diagram(s)sequenceDiagram
participant QSAIndexer
participant QSAStateCache
participant QSAKernels
QSAIndexer->>QSAStateCache: allocate compressed key cache with indexer dtype
QSAIndexer->>QSAKernels: submit matching query and cache dtypes
QSAKernels->>QSAKernels: select dtype-specific launch parameters
QSAKernels-->>QSAIndexer: return selection results
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✅ Passed checks (4 passed)
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Add an opt-in fp8_e4m3 path for the QSA indexer/selector, following the
MiniMax M3 pattern: the normed indexer Q and the compressed K cache share
a plain e4m3 dtype with no scale column (values are GemmaRMSNormed before
caching), and the logits kernels dot fp8 x fp8 directly. Selected via
`attention_config.indexer_kv_dtype` ("bf16" default, "fp8"/"fp8_e4m3"
opt-in, SM90/SM100-family only since Triton cannot multiply fp8e4nv on
SM120/SM121).
The logits Triton kernels themselves are unchanged: tl.dot follows the
pointer dtypes (native fp8 tcgen05 at prefill tile sizes, auto-upcast to
fp16 mma.sync at decode tile sizes on SM100) and the store epilogues
convert implicitly.
Microbenchmark on GB300 (SM103a), indexer logits kernels: decode ~1.9x
bf16 at large batch x context (memory-bound, ~6.9 TB/s), prefill ~1.2x
bf16. See workspace/qwen38-fp8-indexer/RESULTS.md.
Tests: test_qsa_reference.py and test_qsa_pre_indexer.py parametrized
with the fp8 dtype (72 passed). E2E on Qwen/Qwen3.8-Flash-Next: bf16 and
fp8 both pass needle QA at 4.9k/19.5k/39k ctx with matching reasoning
traces and mean prompt logprob deltas <= 0.008.
Co-authored-by: Kimi Code CLI <noreply@moonshot.cn>
Signed-off-by: Thien Tran <gau.nernst@yahoo.com>
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
- Compare fused vs unfused fp8 outputs in uint8 code space (one e4m3 ulp = one code step; sign-magnitude makes code order match value order), with an absolute-tolerance fallback for the denormal range where intermediates differ absolutely due to pooling/norm cancellation - Trim comments; drop unverified claims about SM120-family Triton fp8 support (the gate stays conservative: SM90/SM100-family only) Co-authored-by: Kimi Code CLI <noreply@moonshot.cn> Signed-off-by: Thien Tran <gau.nernst@yahoo.com> Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
fp8e4nv dots work on SM120 too; the capability check was unnecessary. Co-authored-by: Kimi Code CLI <noreply@moonshot.cn> Signed-off-by: Thien Tran <gau.nernst@yahoo.com> Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
fp8 halves the K-tile bytes, shifting the memory-bound optimum of the indexer logits kernels (measured on GB300/SM103a, configs swept on production shapes): - decode: num_warps 2 -> 1 for fp8 (up to 1.21x at dql=4 long-context, neutral at dql=1); bf16 keeps 2 (fp8's choice slightly regresses it) - prefill: TILE_R 64 -> 32 and STAGES 2 -> 3 for fp8 (1.04-1.15x across 8k-128k); bf16 keeps its constants End-to-end select (logits+topk) fp8 vs bf16 on GB300: decode 1.82x (dql=1) / 1.59x (dql=4) at 128k ctx B=512; prefill 1.12-1.15x. Co-authored-by: Kimi Code CLI <noreply@moonshot.cn> Signed-off-by: Thien Tran <gau.nernst@yahoo.com> Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
…ect#54915 kernel The clipped-logits prefill kernel from vllm-project#54915 shifts the fp8 optimum: TILE_R=32 with num_warps=8/STAGES=2 beats the previously tuned warps=4/STAGES=3 by 1.13-1.14x at 32k-128k (GB300/SM103a, in-tree kernel launched with production-shaped clipped logits). bf16 constants unchanged. Co-authored-by: Kimi Code CLI <noreply@moonshot.cn> Signed-off-by: Thien Tran <gau.nernst@yahoo.com> Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
- Drop the fp8_e4m3 spelling from the QSA indexer dtype branch: the IndexerKVDType literal never accepts it, so the branch was dead - De-BF16 the QSA side-cache docstrings now that the dtype is configurable - Add a spec->bind test for the compressed cache in both dtypes Co-authored-by: Kimi Code CLI <noreply@moonshot.cn> Signed-off-by: Thien Tran <gau.nernst@yahoo.com> Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
The test added in vllm-project#55272 drives the unfused path with a SimpleNamespace indexer; it needs the dtype attribute that path reads. Co-authored-by: Kimi Code CLI <noreply@moonshot.cn> Signed-off-by: Thien Tran <gau.nernst@yahoo.com> Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
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The bind guard fails loudly at engine init, so a unit test for the wiring is not worth the lines. Co-authored-by: Kimi Code CLI <noreply@moonshot.cn> Signed-off-by: Thien Tran <gau.nernst@yahoo.com> Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
… comments Co-authored-by: Kimi Code CLI <noreply@moonshot.cn> Signed-off-by: Thien Tran <gau.nernst@yahoo.com> Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
Co-authored-by: Kimi Code CLI <noreply@moonshot.cn> Signed-off-by: Thien Tran <gau.nernst@yahoo.com> Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
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Inline comments:
In `@tests/models/qwen4_exp/test_qsa_pre_indexer.py`:
- Line 61: Update assert_fp8_within_one_ulp to reject non-finite values before
calculating or asserting FP8 code differences, ensuring identical
torch.float8_e4m3fn NaN codes cannot pass the one-ULP check.
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tests/models/qwen4_exp/test_qsa_pre_indexer.pytests/models/qwen4_exp/test_qsa_reference.pyvllm/models/qwen4_exp/common/qsa_cache.pyvllm/models/qwen4_exp/nvidia/indexer_qsa.pyvllm/models/qwen4_exp/nvidia/ops/qsa_indexer.py
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Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
Head branch was pushed to by a user without write access
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✅ Triggered Buildkite CI #87519 for commit |
…54890) Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg> Signed-off-by: Jyotirmoy Roy <jyotirmoyroy649@gmail.com>
Purpose
This PR adds FP8 support for QSA indexer. This implementation doesn't contain any scaling.
Microbenchmarks
All measurements are done on GB300
Decode
Prefill
Generally the speedup is not linear, hinting Triton's inefficiencies. Future PRs can address FP8 performance (I have WIP branches for CuteDSL decode and Triton TMA prefill)
E2E performance
TP4 GB300, 8k-1k
The result is mostly noise because indexer contributes little to e2e timing at short context + we are using BF16 ckpt. TTFT at c=4 is likely an anomaly.
Test Plan
Unit tests
Updated in this PR
E2E tests
BF16 checkpoint, TP4 on GB300. Both with think=false (fast eval)
FP8 is better. Likely within noise
Test Result
Essential Elements of an Effective PR Description Checklist
supported_models.mdandexamplesfor a new model.