[ROCm][Perf] Fuse MiniMax-M3 sparse cache insertion with AITER

[andyluo7]

Summary

• auto-detect AITER's minimax_m3_qknorm_rope_cache_shuffle_insert operation
• use it to fuse MiniMax-M3 sparse-layer QK normalization, RoPE, page-16 K/V insertion, and index-cache insertion
• share the existing page-16 slot-normalization path between the fused and unfused AITER writers
• retain the existing vLLM preprocessing plus reshape_and_cache / index-scatter path when an older AITER build does not provide the operation

This is the vLLM integration for ROCm/AITER #4813. It is confined to the AMD MiniMax-M3 implementation and does not change the CUDA path.

Motivation

The current AITER sparse-paged-attention path runs three stages per sparse layer:

1. vLLM fused QK-norm/RoPE preprocessing
2. AITER reshape_and_cache(..., asm_layout=True) for K/V
3. a separate index-cache scatter

AITER #4813 combines those stages, avoids materializing and rereading normalized K/V through the packed projection buffer, and removes two launches from each sparse layer's hot path.

This PR does not skip the lightning indexer. The full index branch remains active unless vLLM's existing skip_index_topk policy explicitly selects the reuse path.

Compatibility and fallback

• New AITER with Mistral-7B-Instruct-v0.2 inference slows down when implemented on the offline_inference.py example, possibly due to improper usage #4813: the fused operation is selected automatically.
• Older AITER: the import probe returns false and the existing vLLM path runs unchanged.
• Both the full-index and existing skip-index branches are supported.
• BF16 and FP8 main K/V cache modes retain the existing scale contract.
• Both fused and unfused AITER insertion use the existing graph-safe page-16 slot mapping when K/V share block-contiguous storage, and rebuild it for eager or shape-mismatched batches.

No runtime GPU-architecture literal is added here. Before this draft is marked ready, AITER #4813 must either make the operation correct on every supported ROCm architecture where it is exported or expose a capability contract that vLLM can query.

Existing work / non-duplication

• AITER #4813 owns the fused kernel. This PR only wires that public operation into vLLM and deliberately does not duplicate the kernel.
• vLLM #52664 owns AITER indexer selection, FP8 index-query/cache dtype, score/top-k kernels, sparse tables, and related page-layout plumbing. This PR does not carry those changes; it only replaces cache preprocessing/insertion when the fused AITER operation is available.
• vLLM #52849 is now in main and supplies the AITER paged-attention layout used here.
• vLLM #48935 is closed and targets the NVIDIA/internal vLLM kernel path rather than AITER's shuffled page-16 layout.

Composition was checked locally by applying the current #52664 feature delta (92b66b2bdf03) to vLLM main (6cddad414ee4) and then applying this commit (a05636aad5cd). Both cherry-picks completed without conflict. In that combined tree, #52664 retains the FP8 index_q allocation and this PR contributes only fused preprocessing/insertion plus shared slot normalization.

Dependency status

AITER #4813 is currently open at 3def474748bf and is mergeable, but its overall AITER test gate is not green. This vLLM PR remains draft pending a stable AITER landing path and current-head ROCm correctness/evaluation.

Validation

Current rebased vLLM commit:

pre-commit run --files vllm/models/minimax_m3/amd/model.py tests/kernels/attention/test_minimax_m3.py   PASS
.venv/bin/python -m py_compile vllm/models/minimax_m3/amd/model.py tests/kernels/attention/test_minimax_m3.py   PASS
git diff --check origin/main...HEAD   PASS

Three focused regression tests were added for:

• preserving the original slot mapping for separate K/V planes
• reusing graph-safe page-16 metadata for block-contiguous K/V storage
• rebuilding the page-16 mapping for eager or shape-mismatched batches

The focused pytest module was not executed locally: this checkout is on macOS without a ROCm device or the full vLLM test environment, and collection stopped in tests/conftest.py because tblib was absent. It must be run on ROCm before the draft is marked ready.

Prior MI355X evidence, from the earlier vLLM/AITER integration before this rebase:

• direct fused-versus-existing-path smoke passed both the full-index and skip-index branches, with zero maximum absolute error for compared Q, K, V, and index outputs
• full real-target GSM8K completed 1,319/1,319 requests with zero HTTP errors and strict exact match 0.9696739954510993
• controlled AgentX C1 improved median TPOT by 12.9%, median end-to-end latency by 9.8%, and aggregate output throughput by 4.8% to 5,294.14 generated tok/s/chip, with 147/147 measured requests and zero request errors

The GSM8K run also included the separately submitted ROCm unified-attention CUDA-graph metadata fix. These are historical integration results, not current-head signoff; the rebased commit and final AITER dependency still require ROCm reruns.

AI assistance

OpenAI Codex assisted with code analysis, rebasing, focused test construction, static validation, compatibility checking against #52664, and drafting this description. The submitter must review every changed line and run the required ROCm tests before this draft is marked ready for review.

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[Fangzhou-Ai]

Hi @andyluo7 is this PR ready for review? Also do we have any estimated perf gain here?