[Kernel][Perf] Per-architecture tuned configs for batch-invariant persistent matmul (~3x decode kernels on RTX 4090D/H20)

[LioEinaudi]

Purpose

Add per-architecture-family tuned bf16 launch configurations for the
batch-invariant matmul_kernel_persistent path on Hopper and Ada. The table
covers the five Qwen3-1.7B weight shapes, selects BLOCK_SIZE_M,
BLOCK_SIZE_N, num_warps, and num_stages by M bucket, and falls back to
the existing config unchanged for unknown architecture families, shapes, and
dtypes.

BLOCK_SIZE_K is stored once at the (N, K) shape level rather than inside
each M bucket. The bucket data structure cannot express a different reduction
tile, making the invariance-critical constraint—fixed K-reduction order across
M—true by construction.

Architecture-family keys are used per review: hopper values were measured on
H20 (78 SM), and ada values were measured on RTX 4090 D. Selection is
resolved once during batch-invariance initialization from CUDA device
capability: SM 9.x selects hopper, SM 8.9 selects ada, and every other
capability keeps the existing default configuration unchanged.

This follows the profiling and sweep results posted in the batch-invariance
tracker:

• Determinism-tax attribution and kernel bottleneck
• Round 2 tuned-config results and Round 2.1 eager correction

This is not duplicate work with open PR
#49131. That PR adds an
SM80-wide shape heuristic tuned on A100/Qwen2.5 and keeps the original config
for large-M prefill. This change adds offline-swept architecture-family tables
for Hopper and Ada over five Qwen3-1.7B shapes and M=1..2048, including tuned
prefill buckets; the Hopper values were measured on H20 and the Ada values on
RTX 4090 D. Searches for 27433 in:body,
batch invariant matmul tuned configs, and persistent matmul found no other
open PR implementing these tables.

Test Plan

• Run all applicable pre-commit hooks on the three changed Python files,
  including ruff formatting/checks and mypy.

• Run the full existing matmul determinism test file on one RTX 4090 D GPU:

  .venv/bin/python -m pytest \
    tests/v1/determinism/test_matmul_batch_invariant.py -v

• Exercise the tuned table across M=1 versus M in {8, 32, 256, 2048} and
  require bitwise row equality.

• Map capability to the architecture key in the test skip condition. A100
  skips because it has no table entry; Hopper and Ada devices exercise their
  family table. Run the test below on RTX 4090 D.

• Revalidate compiled-mode end-to-end with the final architecture-family
  lookup under TORCH_LOGS=graph_breaks; require the throughput and
  bitwise-invariance gates to pass with no lookup-induced graph break or
  Unsupported.

• Run the full existing batch-invariance test file on the same RTX 4090 D.

• Retain the Round 2 correctness gates: kernel bitwise equality, fp32 reference
  allclose, compiled end-to-end bitwise invariance, and eager end-to-end bitwise
  invariance.

Test Result

Local checks:

pre-commit ruff-check: passed
pre-commit ruff-format: passed
pre-commit markdownlint-cli2: passed
pre-commit run --files (all applicable hooks): passed
pytest --collect-only: 30 tests collected
git diff --check: passed

RTX 4090 D focused pytest, with the changed module source-overlaid on the
precompiled v0.27 CUDA environment:

test_matmul_batch_invariance_across_tuned_m_buckets[8]: PASSED
test_matmul_batch_invariance_across_tuned_m_buckets[32]: PASSED
test_matmul_batch_invariance_across_tuned_m_buckets[256]: PASSED
test_matmul_batch_invariance_across_tuned_m_buckets[2048]: PASSED
30 passed in 9.12s

The full existing batch-invariance suite on the same RTX 4090 D:

19 passed, 35 warnings in 973.32s (0:16:13)

Compiled-mode end-to-end on the same RTX 4090 D, using the final split-module
architecture-family lookup implementation:

lookup preflight: CUDA capability 8.9 -> ada (green)
bi1_compiled throughput: 24.7375 requests/s
acceptance baseline: 25.0600 requests/s (-1.29%, within +/-3%)
compiled invariance probe: green (batch-invariant, bitwise equal)
TORCH_LOGS=graph_breaks: 0 graph breaks, 0 lookup-related hits, 0 Unsupported

Round 2 swept 19,200 points per GPU on vLLM v0.27.0 with Qwen3-1.7B bf16.
All four correctness gates were green on both GPUs. The selected configs changed
decode-kernel geomean versus torch.mm as follows:

GPU	Before	After	Speedup
RTX 4090 D	0.254x	0.768x	3.02x
H20	0.212x	0.593x	2.79x

Prefill kernels improved by 1.16x on RTX 4090 D and 1.11x on H20. Compiled
end-to-end batch-invariance tax also recovered:

GPU	Throughput tax	Latency tax
RTX 4090 D	29.9% -> 21.9%	73.3% -> 35.8%
H20	35.0% -> 31.0%	110.1% -> 59.1%

Round 2.1 found steady-state eager performance neutral on RTX 4090 D (+1.2%).
The one-time warmup cost increased because the persistent matmul specializations
grew from 3 to 43, adding 14.8 seconds during engine initialization; compiled
mode already absorbs this work during graph capture.

AI assistance was used to prepare this implementation and PR text. Before
submission, the human submitter will review every changed line and the focused
GPU test result.

The config table now lives in batch_invariant_configs.py; happy to move to a
JSON-file layout later if preferred.

[claude]

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[LioEinaudi]

Thanks — but the premise doesn't hold on current main: model linear layers never go through those aten overrides in the first place. UnquantizedLinearMethod.apply (vllm/model_executor/layers/linear.py:215-217 at this PR's head) returns linear_batch_invariant(x, layer.weight, bias) whenever VLLM_BATCH_INVARIANT=1 on any CUDA device, so H20 linears reach matmul_persistent() regardless of the SM80-only aten::mm/linear registrations in enable_batch_invariant_mode().

This is also confirmed empirically end-to-end on H20, in the tracker comment linked from the PR description: with BI=1 the torch profiler shows every cuBLASLt nvjet_* GEMM kernel disappear and matmul_kernel_persistent become 79.4% of total kernel time — that attribution is how this kernel was identified as the bottleneck in the first place. The H20 rows in the E2E table above (throughput tax 35.0% -> 31.0%) were measured on H20 serving with this table active.

Agreed that the SM90 branch comment in enable_batch_invariant_mode() ("the only source of batch variance is split-k…") reads as if cuBLAS still handles Hopper GEMMs — linear.py overrides it, which I flagged in the tracker thread. Happy to add a clarifying comment there if maintainers want, but changing that routing is out of scope for this PR.

[yewentao256]

Thanks for the work! We don't want to tune triton for older architecture as it is not used frequently in production. If you are seeking for opportunities to contribute, how about looking some other methods for optimization or doing some model validations?

[LioEinaudi]

Thanks for the quick look, and understood on scope. One small note for context: H20 is current-generation sm90 Hopper rather than an older arch, and most of the reproduction reports in #27433 / #51187 come from exactly this class of community hardware (4090 / 3090 / L20) — but I'm happy to follow your call here. If per-device tables are out of scope I can close this and keep the data in the tracker for reference.

I'd genuinely like to pick up work that's useful to you. Two questions to aim me:

1. For model validations of VLLM_BATCH_INVARIANT: I have RTX 4090 D and H20 available plus a bitwise single-vs-batched probe harness already built (used for the measurements in [Feature]: Batch Invariant Feature and Performance Optimization #27433). Is there a list of models you'd like validated first, and is the issue-per-model format from the tracker still the preferred way to report?
2. On "other methods for optimization": would improvements to the default (arch-generic) config selection for matmul_kernel_persistent be in scope — i.e., better M-bucketed defaults validated on CI hardware — or is that also considered low priority right now?

[yewentao256]

Ohh make sense for hopper, could you test e2e efficient using vllm bench ...? Let's see if it worth the complexity here.

For model validations I don't have a list yet, feel free to test and submit a PR, no issue needed.

Other methods for optimization means something more significant, like #40408

[LioEinaudi]

Ran the E2E benchmarks, mirroring the #40408 format. Setup: vLLM v0.27.0-cu129 (torch 2.13.0), bf16 Qwen3-1.7B; "before" is stock, "after" swaps in this PR's batch_invariant.py (the only runtime file the PR touches — happy to rerun on a main build if you prefer). For each GPU, before and after ran back-to-back in one job on the same physical card (verified via nvidia-smi -q UUID/serial in both phases).

NVIDIA H20

VLLM_BATCH_INVARIANT=1 vllm bench latency --model Qwen/Qwen3-1.7B --input-len 1024 --output-len 128 --batch-size 8

# this PR
Avg latency: 1.1023727376634875 seconds
10% percentile latency: 1.0998693019151689 seconds
25% percentile latency: 1.1000781659968197 seconds
50% percentile latency: 1.1004825318232179 seconds
75% percentile latency: 1.1053236722946167 seconds
90% percentile latency: 1.1057519173249601 seconds
99% percentile latency: 1.1073168623819947 seconds

# before
Avg latency: 1.5623255250354608 seconds
10% percentile latency: 1.556412454135716 seconds
25% percentile latency: 1.5574062908999622 seconds
50% percentile latency: 1.5609258422628045 seconds
75% percentile latency: 1.5667308811098337 seconds
90% percentile latency: 1.569685979001224 seconds
99% percentile latency: 1.5714681649021804 seconds

Avg latency 1.562 s -> 1.102 s (-29.4%, 1.42x).

Batch-size 32, same command otherwise: 2.389 s -> 1.935 s (-19.0%, 1.23x). Throughput (vllm bench throughput, random 512/128, 128 prompts, max-num-seqs 64): 27.06 -> 27.98 req/s (+3.4%).

NVIDIA GeForce RTX 4090 D

Same commands:

# this PR, batch-size 8
Avg latency: 1.594355336887141 seconds
50% percentile latency: 1.5936562579590827 seconds
99% percentile latency: 1.6089839498861693 seconds

# before, batch-size 8
Avg latency: 2.069935770961456 seconds
50% percentile latency: 2.069880980066955 seconds
99% percentile latency: 2.0734073721175084 seconds

Avg latency 2.070 s -> 1.594 s (-23.0%, 1.30x). Batch-size 32: 3.056 s -> 2.553 s (-16.5%, 1.20x). Throughput: 22.38 -> 25.06 req/s (+12.0%).

Correctness

• Bitwise single-vs-batched probe: green (bitwise equal) on both GPUs with the tuned configs, compiled mode.
• Full tests/v1/determinism/test_batch_invariance.py on RTX 4090 D with the PR applied: 19 passed, 35 warnings in 942.99s (0:15:42).

On "worth the complexity": at runtime this is one exact device-name dict lookup plus a scan over at most ten (bound, config) pairs, resolved once at init_batch_invariance(); any miss falls back to the existing config unchanged, so no other device is affected. If you'd prefer a smaller footprint I can cut it down to H20-only. And thanks for the green light on model validations — I'll start submitting those separately.

[yuvalluria]

H100 NVL config proposal (SM90 · 132 SMs · 95 GB HBM3)

Hi @LioEinaudi — I have a single-GPU H100 NVL pod queued in my Azure OCP cluster (vllm-testing namespace) running the sweep now. I'll follow up with raw kernel-level sweep output once the pod gets GPU time. In the meantime, here is a proposed config derived from the H20 sweep data in this PR, plus my reasoning.

Why H100 NVL needs a table entry

H100 NVL is also SM90 (same Hopper tensor-core path as H20), but with 132 SMs vs H20's 78. Without a device-name match, _get_matmul_config falls back to BM=128 BN=128 BK=64 for every M bucket — the same suboptimal config that was causing the 35% throughput tax on H20 before this PR.

Derivation approach

I started from the H20 sweep results and applied two architecture-aware adjustments for H100 NVL:

1. block_k=128 — unchanged; SM90 BF16 tensor-core tile prefers 128 for the K-reduction
2. Small-M buckets (M≤16, decode): identical to H20 — both devices are HBM-bandwidth-bound in decode, so the memory-latency-hiding argument applies equally
3. Large-M buckets (M≥256, prefill): same block shapes as H20 — H100 NVL's higher FMA throughput (1979 vs ~148 BF16 TFLOPS) doesn't change optimal Triton tile shape when the shapes are already register-file limited
4. num_stages: kept equal to H20; both GPUs have the same per-SM shared memory and register file, so stage count arithmetic is identical

Net result: the H100 NVL config is near-identical to H20. The principal benefit of adding the entry is that the device-name lookup succeeds; the specific block sizes will be refined by the measured sweep.

Proposed H100 NVL config entry

    "NVIDIA H100 NVL": {
        (12288, 2048): _MatmulShapeConfig(
            block_k=128,
            m_buckets=(
                (1,    _MatmulMConfig(16, 256, 4, 3)),
                (4,    _MatmulMConfig(16, 256, 4, 4)),
                (8,    _MatmulMConfig(16,  64, 4, 4)),
                (16,   _MatmulMConfig(16,  64, 4, 4)),
                (32,   _MatmulMConfig(32,  64, 8, 5)),
                (64,   _MatmulMConfig(64,  64, 4, 4)),
                (256,  _MatmulMConfig(64, 128, 4, 3)),
                (512,  _MatmulMConfig(128,128, 8, 3)),
                (1024, _MatmulMConfig(128,256, 8, 2)),
                (2048, _MatmulMConfig(128,256, 8, 2)),
            ),
        ),
        (2048, 6144): _MatmulShapeConfig(
            block_k=128,
            m_buckets=(
                (1,    _MatmulMConfig(16,  32, 4, 4)),
                (4,    _MatmulMConfig(16,  64, 4, 4)),
                (8,    _MatmulMConfig(16,  64, 4, 4)),
                (16,   _MatmulMConfig(16,  32, 4, 3)),
                (32,   _MatmulMConfig(32,  32, 8, 3)),
                (64,   _MatmulMConfig(64,  32, 4, 5)),
                (256,  _MatmulMConfig(64, 128, 4, 3)),
                (512,  _MatmulMConfig(128,128, 4, 3)),
                (1024, _MatmulMConfig(64,  64, 4, 5)),
                (2048, _MatmulMConfig(64, 128, 4, 4)),
            ),
        ),
        (4096, 2048): _MatmulShapeConfig(
            block_k=128,
            m_buckets=(
                (1,    _MatmulMConfig(16,  64, 8, 5)),
                (4,    _MatmulMConfig(16,  64, 4, 5)),
                (8,    _MatmulMConfig(16, 128, 4, 3)),
                (16,   _MatmulMConfig(16,  64, 4, 5)),
                (32,   _MatmulMConfig(16,  64, 4, 4)),
                (64,   _MatmulMConfig(64,  32, 4, 3)),
                (256,  _MatmulMConfig(64, 256, 4, 2)),
                (512,  _MatmulMConfig(64,  64, 4, 3)),
                (1024, _MatmulMConfig(64, 128, 4, 3)),
                (2048, _MatmulMConfig(64,  64, 4, 4)),
            ),
        ),
        (151936, 2048): _MatmulShapeConfig(
            block_k=128,
            m_buckets=(
                (1,    _MatmulMConfig(16, 256, 4, 4)),
                (4,    _MatmulMConfig(16, 256, 4, 4)),
                (8,    _MatmulMConfig(16, 256, 4, 3)),
                (16,   _MatmulMConfig(16, 256, 4, 3)),
                (32,   _MatmulMConfig(32, 256, 8, 3)),
                (64,   _MatmulMConfig(64, 128, 4, 3)),
                (256,  _MatmulMConfig(64, 128, 4, 3)),
                (512,  _MatmulMConfig(128,128, 8, 3)),
                (1024, _MatmulMConfig(128,256, 8, 2)),
                (2048, _MatmulMConfig(128,256, 8, 2)),
            ),
        ),
        (2048, 2048): _MatmulShapeConfig(
            block_k=128,
            m_buckets=(
                (1,    _MatmulMConfig(16,  64, 4, 5)),
                (4,    _MatmulMConfig(16, 128, 8, 3)),
                (8,    _MatmulMConfig(16,  32, 4, 3)),
                (16,   _MatmulMConfig(32,  64, 8, 5)),
                (32,   _MatmulMConfig(16, 128, 4, 5)),
                (64,   _MatmulMConfig(32,  64, 4, 2)),
                (256,  _MatmulMConfig(128, 64, 4, 4)),
                (512,  _MatmulMConfig(64, 256, 4, 2)),
                (1024, _MatmulMConfig(64,  64, 4, 3)),
                (2048, _MatmulMConfig(64, 128, 4, 3)),
            ),
        ),
    },

Expected E2E impact

H100 NVL has the same SM90 tensor-core path as H20 and the same batch-invariance bottleneck (matmul_kernel_persistent dominates when VLLM_BATCH_INVARIANT=1). Based on the H20 numbers in this PR:

Metric	H20 (measured, PR)	H100 NVL (expected, SM90 analogue)
Avg latency before (bs=8)	1.562 s	TBD — sweep running
Avg latency after (bs=8)	1.102 s	TBD — sweep running
Improvement	−29.4%	Similar class expected

I will update this with actual vllm bench latency numbers from the H100 NVL pod once it completes.

Device-name string

The device name returned by get_device_name() on my Azure H100 NVL node is expected to be "NVIDIA H100 NVL" — I'll confirm the exact string from the pod output and adjust the key if needed.

Offer

Happy to add this entry directly to your PR (you have my sign-off on the config), or I can open a follow-up PR once the measured sweep data is in. Let me know which you prefer.

---

AI assistance used to derive this config from the H20 sweep data and prepare this comment. Reviewed and proposed by yuvalluria (Red Hat, working toward vLLM contributor status, mentored by @yewentao256).

[yewentao256]

Wow, very good perf improvement I didn't think about before, nice work.

[yewentao256]

This file is expanding, let's put this in other file.

[LioEinaudi]

Done in efb71fe — moved to batch_invariant_configs.py.

[yewentao256]

I think we should have something more broad, like hopper, blackwell instead of specific device.

[LioEinaudi]

Done in efb71fe — keyed by architecture family now (hopper/ada, resolved from CUDA capability at init). hopper values are measured on H20, ada on RTX 4090 D.

[yewentao256]

Suggested change

	### Eager-mode Warmup
	On devices and weight shapes with tuned persistent matmul configurations,
	run one representative workload as a warmup before measuring eager-mode
	steady-state performance. For Qwen3-1.7B, the tuned path increases the number of
	Triton specializations for this kernel from 3 to 43 and adds approximately 15
	seconds of one-time engine initialization. Compiled mode already absorbs this
	work during graph capture.

This doc is not needed

[LioEinaudi]

Removed

[yuvalluria]

Thanks for the feedback @WentaoYe-Redhat! Following your review comments:

1. Architecture-based naming — completely agree, "Hopper" (SM90) is cleaner and covers all H100 variants (NVL, SXM, PCIe). Updated proposed config:

# In a separate config file (e.g., vllm/model_executor/layers/batch_invariant_configs.py)
"Hopper": _MatmulShapeConfig(
    block_k=128,
    m_buckets=(
        (1,   _MatmulMConfig(block_m=16,  block_n=64,  num_warps=4, num_stages=3)),
        (2,   _MatmulMConfig(block_m=16,  block_n=64,  num_warps=4, num_stages=3)),
        (4,   _MatmulMConfig(block_m=16,  block_n=128, num_warps=4, num_stages=3)),
        (8,   _MatmulMConfig(block_m=32,  block_n=128, num_warps=4, num_stages=3)),
        (16,  _MatmulMConfig(block_m=64,  block_n=128, num_warps=4, num_stages=4)),
        (32,  _MatmulMConfig(block_m=64,  block_n=128, num_warps=4, num_stages=4)),
        (64,  _MatmulMConfig(block_m=128, block_n=128, num_warps=8, num_stages=4)),
        (128, _MatmulMConfig(block_m=128, block_n=256, num_warps=8, num_stages=3)),
        (256, _MatmulMConfig(block_m=128, block_n=256, num_warps=8, num_stages=3)),
        (512, _MatmulMConfig(block_m=128, block_n=256, num_warps=8, num_stages=3)),
    ),
),

2. Separate file — agreed, happy to move the config dict out of batch_invariant.py.

Should I open a follow-up PR with the Hopper config (in a separate file, using architecture names) once this one merges? Or would you prefer I add it directly here?

[LioEinaudi]

@yuvalluria Thanks for the interest! I’d suggest a follow-up PR once your H100 NVL sweep actually completes — measured numbers kept this PR alive, and I’d rather not fold in derived entries under the same evidence bar. The refactor requested in review (separate config file + arch-family keys) has now landed here, so your addition becomes a data-only change on top. Looking forward to the raw sweep output.

[yewentao256]

LGTM, thanks for the work! I will do some perf tuning and refactor after this PR landed

[github-actions]

✅ @LioEinaudi, CI is now available for this PR.

• /ci run starts upstream CI; /amd-ci run starts AMD CI only.
• /ci retry retries failed jobs in the CI build for the current PR head. If the current head has no CI build, it starts a new CI build for the current head containing only jobs that failed in the latest earlier CI build for this PR.
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[LioEinaudi]

/ci run

[github-actions]

✅ Triggered Buildkite CI #85246 for commit 19d32587ee84.

[LioEinaudi]

/ci retry

[github-actions]

✅ Queued 1 failed job(s) for retry in Buildkite CI #85246.

[LioEinaudi]

Following up on the model-validation invitation: first batch opened as #53692 (google/gemma-3-1b-it,zai-org/glm-4-9b-chat, microsoft/phi-4 — bitwise probe green in both compiled and eager on RTX 4090 D / H20).