[Kernel][MoE] Add VMM-backed SharedEP for native FP4 decode on SM100

[foraxe]

[Kernel][MoE] Add VMM-backed SharedEP for native FP4 decode on SM100

Summary

This adds a shared_ep all-to-all backend for low-latency MoE decode on peer-accessible SM100 GPUs.

The conventional dispatch/combine path materializes both communication
boundaries:

router
  -> pack and dispatch routed activations
  -> materialized expert-rank input
  -> expert W1/W2
  -> materialized rank-partial output
  -> combine and reduce
  -> owner output

SharedEP publishes persistent, peer-addressable objects instead:

router
  -> owner quantizes into fixed VMM rows and publishes routes
  -> expert rank gathers NVFP4 rows into the local layout required by W1
  -> unchanged native W1/W2
  -> W2 writes directly into canonical owner/token/top-k VMM slots
  -> owner-local top-k reduction

The backend creates persistent rank-major CUDA VMM objects during model setup. Each rank owns one physical allocation per object, exchanges its POSIX allocation handle once over the CPU process group, and maps every owner allocation into a stable rank-major virtual address range. Typed owner views and persistent device pointer tables are also created once during setup.

There is no allocation, handle exchange, VMM mapping, pointer-table construction, or peer-tensor initialization in the model forward path. Runtime execution consists of native quantization, direct peer loads/stores, and system-scope GPU release/acquire epochs.

The selected backend fails closed. In particular, NVFP4 requires the exact
FlashInfer direct-output API and refuses to materialize a rank-partial W2
fallback. It does not switch to another EP backend, expert kernel, or
quantization path.

Native GB200 paths

• GLM-5.2: BF16 owner input is quantized to native NVFP4, fixed owner-reserved rows are gathered through the VMM peer view into the contiguous local-HBM layout required by FlashInfer CuTeDSL, local experts execute, and the W2 finalize epilogue stores every expanded token/top-k contribution directly into its canonical owner VMM row.
• DeepSeek-V4-Flash: owner input is quantized to native MXFP8 with UE8M0 scales, the same fixed owner-reserved rows are gathered, FlashInfer TensorRT-LLM MXFP4/MXFP8 experts execute, and partial outputs are directly scattered into owner slots.

After all source ranks publish their output epoch, an NVFP4 owner reduces only
its local top-k slots. This removes the W2 output memset, rank-partial W2
tensor, remote output scatter, peer pull of four rank-partial tensors, and
world-rank output reduction. MXFP8 retains its existing rank-partial
scatter/reduction path.

This is adapted from SGLang PR #32482 with source attribution. That source PR was tested on H20, which has no native NVFP4 hardware path. This port intentionally uses the native NVFP4 and MXFP4/MXFP8 paths available on GB200 and in the local checkpoints.

Scope and admission

shared_ep currently requires:

• one peer-accessible SM100 NVLink domain with native peer atomics;
• TP=1;
• DP/EP greater than one, with every DP/EP rank local to that domain;
• at most 32 scheduled tokens per rank;
• chunked prefill;
• no DBO/ubatching, EPLB, elastic EP, fault tolerance, or multi-node execution;
• the exact native NVFP4/CuTeDSL or MXFP4/MXFP8/TRT-LLM expert backend selected by the checkpoint.

Unsupported configurations raise an admission error.

Relationship to #50009

vLLM PR #50009 owns the reusable RankMajorPeerView and create_rank_major_peer_view CUDA VMM implementation. This feature branch is stacked directly on that PR and imports those helpers; the generic VMM implementation is not duplicated in this feature diff.

The current feature commit is 35395b1d0b345fafea6b5640ac7750bb5cee7d9a. Its local dependency base a3400f39a merges #50009 head f5c8cc4c1 with vLLM main e04a30a77. The feature-only range is 21 files, 2,020 insertions, and 9 deletions. GitHub displays the unmerged #50009 stack in this draft as well, so the complete PR view is currently 39 files.

#50009 is the deliberate infrastructure dependency; no generic CUDA VMM implementation is duplicated here.

Validation

Current-base CPU and four-GPU GB200 coverage:

• focused vLLM suite: 40 passed, 14 warnings in 40.68 s;
• same-allocation owner-pull distributed control: 2 passed, 14 warnings in 21.78 s;
• current FlashInfer direct-owner test: 1 passed, 380 deselected in 6.37 s after its one-time build;
• applicable changed-file pre-commit hooks and git diff --check passed in both repositories.

The strict GLM-shape EP4 matrix used 20 warmups, 100 captured iterations per
trial, five trials, and T=1/4/16/32. Direct W2 measured
55.303/65.721/105.230/151.178 us versus paired same-VMM-allocation
owner-pull 57.443/67.922/107.438/154.044 us, saving
2.141/2.201/2.209/2.866 us or 3.73/3.24/2.06/1.86%. Independent-reference
maximum absolute error remained 0.25; eager repeat, graph replay, and
graph-versus-eager checks were exact.

Model correctness and performance

Hardware: four NVIDIA GB200 GPUs in one NV18 peer-accessible domain.

The request-level protocol is EP4, batch one per rank, exactly 128 input and
128 greedy output tokens with ignore_eos, three warmups, five measured
trials, full/piecewise CUDA graphs with capture sizes 1/4/16/32, and
maximum-rank aggregation.

GLM-5.2 backend/output boundary	Median TTFT	Median TPOT	Median elapsed	Rank-0 consumed memory	Rank-0 KV tokens
SharedEP direct W2	139.513 ms	14.305 ms/token	2361.013 ms	130.62 GiB	725696
SharedEP owner-pull control	137.187 ms	14.740 ms/token	2424.229 ms	132.24 GiB	706368
DeepEP low latency	139.657 ms	17.193 ms/token	2811.797 ms	133.93 GiB	669760

Direct W2 versus owner-pull saves 0.435 ms/token (2.95%) and 63.216 ms
elapsed (2.61%), while TTFT is 2.327 ms slower. The complete SharedEP path
versus DeepEP low latency saves 2.888 ms/token (16.80%) and 450.783 ms
elapsed (16.03%); TTFT differs by 0.144 ms.

Maximum-rank TPOT trial vectors:

• direct W2: 14.3023/14.3077/14.3045/14.3052/14.3049 ms/token;
• owner-pull: 14.7377/14.7355/14.7400/14.7449/14.7497 ms/token;
• DeepEP low latency: 17.1884/17.1918/17.1933/17.1927/17.1905 ms/token.

Every backend produced the same 128 greedy tokens on every rank and trial: the
sequence [576, 6722, 315, 9621, 374, 12089, 13, 220] repeated 16 times.

The owner-pull control uses the same direct-output VMM allocation but executes
FlashInfer's ordinary atomic finalize path. Its activation and CUDA-graph
accounting is therefore higher; "same allocation" does not mean identical
whole-engine memory use.

Current-base DeepSeek-V4-Flash SharedEP versus DeepEP-v2 timing is WIP. The
installed vLLM environment carries NCCL 2.29.7, so the DeepEP-v2 arm uses an
isolated nvidia-nccl-cu13==2.30.7 package. DeepEP 2.0 imports with its
duplicate-runtime check enabled, vLLM reports runtime NCCL 2.30.7,
has_deep_ep_v2() passes, and /proc/self/maps contains only the isolated
2.30.7 library. The first current-base DSV4 arm was interrupted before
measurement when four unrelated GPU occupier jobs began using every GPU; no
timing from that attempt is accepted.

Reproduction:

CUDA_VISIBLE_DEVICES=0,1,2,3 \
PYTHONPATH=$PWD \
.venv/bin/python benchmarks/benchmark_shared_ep.py \
  --model /path/to/model \
  --backend shared_ep \
  --world-size 4 \
  --input-len 128 \
  --output-len 128 \
  --warmup 3 \
  --repeats 5 \
  --kv-cache-dtype fp8

Use --backend deepep_low_latency for the GLM-5.2 baseline and --backend deepep_v2 for the DeepSeek-V4-Flash baseline. GLM-5.2 does not require --kv-cache-dtype fp8.

Greedy-ID agreement is a bounded correctness gate, not a full accuracy
evaluation. Full model accuracy evaluation and the current-base DSV4 pair
remain WIP.

Bounded optimization decisions

The PR keeps one fixed owner-reserved input layout and one local-HBM
gather. Eliminating that final input materialization requires a separate
owner-aware indexed NVFP4 W1 kernel that pipelines peer loads with tensor-core
work. That larger kernel project is intentionally not hidden inside this first
SharedEP PR.

Dependencies

This change depends on vLLM PR #50009 for the generic rank-major CUDA VMM
peer-view abstraction and FlashInfer PR
flashinfer-ai/flashinfer#4268 for CuTeDSL NVFP4 direct
owner output. Both dependencies must land or be pinned before SharedEP NVFP4
can be enabled.

AI assistance

AI assistance was used to port, implement, test, benchmark, and prepare this change. The submitting human must review every changed line, rerun or independently accept the validation, and be able to explain and defend the VMM lifetime, owner layout, GPU epoch protocol, native kernel selection, and fail-closed admission behavior before publication.

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[mergify]

Documentation preview: https://vllm--50392.org.readthedocs.build/en/50392/

[mergify]

This pull request has merge conflicts that must be resolved before it can be
merged. Please rebase the PR, @foraxe.

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