[XPU] Route INC WNA16 MoE to oracle backend instead of bf16 dequant

[sgurwinderr]

Purpose

On XPU, loading an INC (AutoRound) int4 MoE checkpoint OOMs at model load because INCWna16Scheme.get_moe_method returns UnquantizedFusedMoEMethod, materializing every expert as full bf16. For example, Intel/Qwen3-30B-A3B-Instruct-2507-int4-AutoRound fails to load on a 24GB card (Arc Pro B60). XPU already has a working quantized MoE path — the WNA16 oracle backend (XPUExpertsWNA16, added in #41426) — so the dequant fallback is both wasteful and broken on memory-constrained cards.

Root cause

get_moe_method short-circuited with if current_platform.is_xpu() or current_platform.is_cpu(): return UnquantizedFusedMoEMethod(...) before reaching _resolve_gptq_moe, which builds the MoeWNA16Method that dispatches through the oracle to XPUExpertsWNA16. Separately, _resolve_gptq_moe computes use_marlin via check_moe_marlin_supports_layer, which is platform-agnostic — so even after falling through, XPU could pick AutoGPTQMoEMethod (Marlin, torch.ops._C, CUDA-only).

Fix

• Drop XPU from the dequant early-return (keep CPU, which has no quantized MoE path yet), so sym-int4 GPTQ/AutoRound flows to _resolve_gptq_moe.
• Gate use_marlin off for XPU in _resolve_gptq_moe so XPU takes the MoeWNA16Method (oracle → XPUExpertsWNA16) path rather than the CUDA-only Marlin method.

Test plan

Verified on Arc Pro B60 (BMG) with Intel/Qwen3-30B-A3B-Instruct-2507-int4-AutoRound, --enforce-eager, max_model_len=2048:

• Before: OOM at load — Failed to load model - not enough GPU memory ... Using XPU Unquantized MoE backend.
• After: loads within the card's memory and generates correctly ("The capital of France is Paris. ...") via the WNA16 oracle backend.

The kernel dependencies for the XPU WNA16 path (vllm-xpu-kernels moe_align/silu fixes) are satisfied by the pinned kernels version.

Risk

XPU-only behavior change, gated by current_platform.is_xpu()/is_cpu(). CPU keeps its existing dequant fallback; CUDA/ROCm Marlin selection is unchanged. The XPU path it routes to is the one already used for AWQ/GPTQ MoE on XPU.

Fixes #47937.

[claude]

Claude Code Review

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[sgurwinderr]

Verified on Arc Pro B60 (BMG): with Intel/Qwen3-30B-A3B-Instruct-2507-int4-AutoRound, --enforce-eager, the stock path OOMs at load (UnquantizedFusedMoEMethod → bf16 experts) while this change loads and generates correctly via the WNA16 oracle backend.

The buildkite/intel-ci red mark (Build #6717) is the unlabeled outside-contributor gate, not a test failure on the change — a reviewer adding the ready/verified label should let full CI run.

[yma11]

@yiliu30 Can you take a look this change?

[yiliu30]

Hi @sgurwinderr, this part looks good to me. Thanks for the fix!

There is a similar fix in #47124.

[yiliu30]

For this part, do we really need this gate? AutoGPTQMoEMethod should support XPU as well, right?
Can we leave it as is and leverage AutoGPTQMoEMethod to construct the WNA16 method for XPU?

[mayuyuace]

Vllm-xpu-kernels uses XPUExpertsWNA16, so here is expected.

[mayuyuace]

LGTM.
@jikunshang Please help review this PR.

[urakozz]

Hey guys alarm! I was experimenting with MoE model on the Intel Arc B70 with the main code + this PR and found something - it will break the code (and I have a fix). It looks like this branch was started before #44120 has landed

With a Qwen3.5-MoE-35B checkpoint quantized via auto-round (--format auto_round, W4A16, group_size=64, sym) -> so a different model family and group size than tested here -> stock main OOMs at load exactly as described (Using XPU Unquantized MoE backend-> bf16 experts). With this PR applied, the experts route to the WNA16 oracle and the model loads at 18.7 GiB.

On current main (anything including ec59c15 / #44120, merged Jul 21 after this PR's validation), the MoeWNA16Method route crashes at the first MoE forward:

  RuntimeError: ptr_scales.size(1) of int4 must match N                                                                                                                
    (torch.ops._xpu_C.cutlass_grouped_gemm_interface, via XPUExpertsWNA16)

What I found finally:

 Root cause: #44120 routed MoeWNA16Method.process_weights_after_loading through convert_to_wna16_moe_kernel_format, whose XPU branch unconditionally calls            
  _process_weights_xpu. That helper's contract is the AutoGPTQ K-first layout (scales [E, K//group_size, 2N]), but MoeWNA16Method registers N-first tensors (w13 [E,   
  2N, K//2] uint8, scales [E, 2N, K//group_size]) — which are already the layout xpu_fused_moe(is_int4=True) consumes. The unconditional transpose flips them, and the 
  kernel's shape check fires (e.g. size(1) = K//gs = 32 vs N = 1024 for this model). Notably, #44120's TRITON branch discriminates the MoeWNA16 source layout ("N-first
  → no-op"), but the XPU branch doesn't — this affects every MoeWNA16Method use on XPU since that merge, not just this PR's routing.

@sgurwinderr feel free to fold this into the PR or if the maintainers prefer, it can go as a separate bugfix against #44120 since the breakage is independent of this PR. I tried main code + this PR + my patch - Qwen3.6 35B A3B with Intel's Autoround int4 finally fits 32GB

XPU-Keep-MoeWNA16-s-N-first-layout-in-WNA16-o.patch

[mayuyuace]

Models--meta-llama--Llama-3.2-1B-Instruct failed in the CI.
This should be a bug in main branch.

[urakozz]

@mayuyuace I guess bug is here as well (another one probably), check patch from my previous comment - after refactoring there are now checks in the code for MoeWNA16Config. I have main code + this branch + my patch - everything works on Intel B70. Without my patch on top it doesn't. (Qwen3.6 35B int4 autoround / mxfp4)

[sgurwinderr]

Thanks all — I've reworked this. Summary of what changed and why:

Removed the XPU gate in _resolve_gptq_moe (@yiliu30, you were right). My premise was wrong: check_moe_marlin_supports_layer isn't platform-agnostic (it already has a ROCm guard, marlin_utils.py:365-366), and more decisively AutoGPTQMoEMethod never reaches Marlin on XPU anyway — _get_priority_backends() returns [WNA16MoEBackend.XPU] (int_wna16.py:112-115) and MarlinExperts._supports_current_device() requires CUDA (marlin_moe.py:610-612). So no XPU gate was needed. That function is now byte-identical to main.

intel-ci was my fault, and this fixes it. Build 7457's test_resolve_gptq_moe_uses_auto_gptq_when_supported failure came from my gate diverting a test that patches both Marlin checks but not is_xpu. @mayuyuace — I think the earlier comment mixed up two jobs: the screenshot is buildkite/ci/pr/model-executor (dense Llama-3.2-1B, H200/CUDA, LoRA — no MoE/XPU/INC, no causal path from this PR); intel-ci was the separate, real, PR-caused one.

@urakozz — #44120 diagnosis confirmed, taking it separately. The oracle's XPU branch is the only backend branch with no source-layout check (TRITON checks positively at int_wna16.py:1603-1631, CPU raises, HUMMING uses isinstance); _process_weights_xpu expects AutoGPTQ's K-first int32 and transposes unconditionally, while MoeWNA16Method hands it N-first uint8. It affects every MoeWNA16Method XPU user since #44120, not just this path, so it deserves its own cherry-pickable PR — happy for you to open it, else I will and credit you. One correction: XPUExperts.apply never forwards zero-points (xpu_moe.py:160-176), so passing qzeros through would turn a loud assert into silent numerical corruption on asym checkpoints — please reject has_zp explicitly.

Added a guard so this PR can't newly reach that broken path. Removing the blanket bf16 dequant makes MoeWNA16Method → oracle-XPU reachable, so get_moe_method now pre-checks the same two conditions _resolve_gptq_moe uses and keeps the bf16 fallback otherwise. Note this matters for the target model itself at TP>=4 (768/4 = 192, not a multiple of 128). Added 3 tests; get_moe_method had none before.

@lkk12014402 — #47124 contains this PR's first hunk verbatim and the opposite of the gate I just removed. Suggest landing this smaller one first and rebasing yours.

Known gap, not fixed here: the Xe2 arch check in XPUExperts.__init__ isn't part of is_supported_config, so pre-Xe2 Intel GPUs lose the bf16 fallback. That's oracle-side and belongs with the fix above.

@jikunshang — diff changed materially since your approval, could you re-review?

[urakozz]

@sgurwinderr It looks like my catch was taken care of in #50209, thx for double checking and confirming!

[mergify]

This pull request has merge conflicts that must be resolved before it can be
merged. Please rebase the PR, @gurwinderintel.

https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/working-with-forks/syncing-a-fork

[mayuyuace]

After PR #47124 is merged, INC model will choose AutoGPTQConfig/AutoAWQConfig for MOE backend. Bug is fixed.

@sgurwinderr @urakozz
Please check.

[sgurwinderr]

Closing this — #47124 landed first and supersedes it. Thanks @lkk12014402; your PR carries the same get_moe_method change, and it went further by dropping check_marlin_supported from _resolve_gptq_moe so the XPU path is reachable for (8, True) too. Rebasing this branch would only revert that, so there's nothing left worth merging here.

For the record, the reworked version of this PR did go green: intel-ci #7715 passed, and model-executor passed as well, which confirms the earlier test_sharded_state_loader failure was unrelated to this change.

Thanks @yiliu30, @mayuyuace, @urakozz and @jikunshang for the reviews. One loose end I've raised on #50209 rather than here — I don't think the MoeWNA16Config layout issue is fully closed on main yet.