[Model][Hardware][AMD]: Part 1/2 -> Enable e2e QK Norm + RoPE + KV Cache runtime fusion for Qwen3-30B-A3B on ROCM_AITER_FA, and ROCM_AITER_UNIFIED_ATTN by jhu960213 · Pull Request #42749 · vllm-project/vllm

jhu960213 · 2026-05-15T14:53:22Z

Purpose

This is Part 1 of a stacked PR series that splits the original
jhu96/optimize-qwen30b branch (PR: #39527) into two reviewable PRs.

Here, we enabled runtime inductor fusion substitution for both the ROCM_AITER_FA and ROCM_AITER_UNIFIED_ATTN attention backends. As for ROCM_ATTN (coming in part 2), it requires kernel-level changes, thus deferring to another PR.
Enable e2e runtime QK Norm + RoPE + KV Cache fusion for Qwen3-30B. At compile time, we swap the aforementioned fusion pattern & fuse with aiter's high-performance HIP kernel fused_qk_norm_rope_cache_pts_quant_shuffle for all decoder layers that satisfy a preset token compile range guarded by rope_kvcache_fusion_max_token_num.

Test Plan

To test this fusion out, please pass the attached toggle through the pass config under the --compilation-config when launching with vllm serve:

'pass_config': { 'fuse_qk_norm_rope_kvcache': True, 'rope_kvcache_fusion_max_token_num': 256 }

For example, something like this:

VLLM_ROCM_USE_AITER=1 \ vllm serve /path-to-your/Qwen3-30B-A3B \ --host 0.0.0.0 \ --port 8080 \ --attention-backend ROCM_ATTN \ --no-enable-prefix-caching \ -O1 \ --compilation-config '{ "pass_config": { "fuse_qk_norm_rope_kvcache": true, "rope_kvcache_fusion_max_token_num": 256 } }

In addition, one can verify the unit test for this fusion with:
pytest tests/compile/passes/test_qk_norm_rope_kvcache_fusion.py -v
`

Test Result

Adds the QkNormRopeKvCacheFusionPass and the torch.ops.vllm.fused_qk_norm_rope_and_unified_kv_cache_update custom op that backends opt into via fused_qk_norm_rope_kvcache_supported(). The pass matches the split(QKV) -> RMSNorm -> RoPE -> unified_kv_cache_update sequence and replaces it with a single fused AITER HIP kernel call (fused_qk_norm_rope_cache_pts_quant_shuffle) on ROCm with AITER. Pass wiring: - Adds pass_config.fuse_qk_norm_rope_kvcache (auto-enabled at O1+ on ROCm for QK-norm models like Qwen3 / Qwen3-MoE) and rope_kvcache_fusion_max_token_num to PassConfig. - Adds enable_qk_norm_rope_kvcache / enable_qk_norm_rope optimization- level callables. - Registers the pass in PostGradPassManager. IR refactor companion edits: - matcher_utils.py: adds MatcherRMSNorm that dispatches through ir.ops.rms_norm so the pattern follows the same backend (native / vllm_c / aiter / oink / ...) chosen by IrOpPriorityConfig (after the vLLM IR migration in PR vllm-project#33825), removing the need to register per- backend RMS variants. - qk_norm_rope_fusion.py: routes the existing QK-norm + RoPE pass through MatcherRMSNorm so it benefits from the same IR dispatch. - act_quant_fusion.py: guards FP8 group quant op registration on the presence of silu_and_mul_per_block_quant, which is not built on all platforms. Signed-off-by: Jack Hu <Jack.Hu@amd.com>

…M_AITER_UNIFIED_ATTN backends Adds the backend dispatch surface for the fused QK-norm + RoPE + KV-cache pass introduced in the previous commit: - AttentionImpl base class (backend.py) gains three new hooks that default to a disabled, non-implemented state: fused_qk_norm_rope_kvcache_supported() -> False set_fused_kv_cache_layout() -> pass do_qk_norm_rope_kvcache_update(...) -> raise NotImplementedError - rocm_aiter_ops.hip_qk_norm_rope_and_cache wraps AITER's fused_qk_norm_rope_cache_pts_quant_shuffle so the per-backend do_qk_norm_rope_kvcache_update bodies share a single call site. - ROCM_AITER_FA (rocm_aiter_fa.py) opts in: fused_qk_norm_rope_kvcache_supported() -> rocm_aiter_ops.is_enabled() set_fused_kv_cache_layout() -> no-op do_qk_norm_rope_kvcache_update(...) calls hip_qk_norm_rope_and_cache with use_shuffle_layout = is_shuffle_kv_cache_enabled() and caches k_scale/v_scale CPU tensors lazily so the C++ kernel's .item() does not trigger a host sync during CUDA graph capture. - ROCM_AITER_UNIFIED_ATTN (rocm_aiter_unified_attn.py) inherits do_qk_norm_rope_kvcache_update from RocmAttentionImpl and adds two overrides so it engages the fused path despite the parent being gated off: fused_qk_norm_rope_kvcache_supported() -> rocm_aiter_ops.is_enabled() set_fused_kv_cache_layout() -> no-op (this backend uses the AITER triton unified attention kernel for decode, not the custom HIP ASM paged attention kernel, so it doesn't need interleaved V). - ROCM_ATTN (rocm_attn.py) ships the full do_qk_norm_rope_kvcache_update implementation (so UNIFIED ATTN can inherit it) but keeps fused_qk_norm_rope_kvcache_supported() returning False. ROCM_ATTN itself will opt in via a follow-up PR that adds USE_INTERLEAVED_V_CACHE to the custom HIP paged-attention decode kernel and the matching INTERLEAVED_V_KX path in prefix_prefill, since the AITER fused write produces V in interleaved layout for that backend. Signed-off-by: Jack Hu <Jack.Hu@amd.com>

Adds tests/compile/passes/test_qk_norm_rope_kvcache_fusion.py covering: - test_qk_norm_rope_kvcache_fusion: full correctness check that compares q / k / v outputs and the K-cache (plus V-cache when no interleaving is in effect) of the fused compiled graph against the unfused eager forward, parametrized over ROCM_AITER_FA and ROCM_AITER_UNIFIED_ATTN x AITER triton rope x num_heads / kv_heads / head_size / block_size / is_neox / dtype / kv_cache_dtype / rms_norm_eps. - test_qk_norm_rope_kvcache_pattern_match_smoke: fast smoke check that just verifies the pattern matcher finds and replaces the unfused pattern exactly once, useful for iterating on the matcher itself. The smoke test uses ROCM_AITER_UNIFIED_ATTN. ROCM_ATTN is added to the parametrize list in the follow-up PR that enables fusion for it. Signed-off-by: Jack Hu <Jack.Hu@amd.com>

github-actions · 2026-05-15T14:53:34Z

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mergify · 2026-05-15T14:54:33Z

This pull request has merge conflicts that must be resolved before it can be
merged. Please rebase the PR, @jhu960213.

https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/working-with-forks/syncing-a-fork

Signed-off-by: Jack Hu <Jack.Hu@amd.com>

gemini-code-assist

Code Review

This pull request introduces the QkNormRopeKvCacheFusionPass, which fuses QK-normalization, Rotary Positional Embeddings (RoPE), and KV cache updates into a single AITER HIP kernel for ROCm platforms. This optimization aims to reduce kernel launch overhead and memory traffic for models that utilize QK-norm, such as Qwen3 and Qwen3-MoE. The changes include the fusion pass implementation, new pattern matchers for RMSNorm, and updates to the compilation configuration to auto-enable these fusions. Feedback from the reviewer correctly pointed out that scale tensors should be explicitly created on the CPU to prevent performance-degrading device-to-host synchronizations during CUDA graph capture.

I am having trouble creating individual review comments. Click here to see my feedback.

vllm/v1/attention/backends/rocm_aiter_fa.py (1526)

The scale tensor should be explicitly created on the CPU to avoid potential device-to-host synchronizations when the C++ kernel calls .item(). If torch.set_default_device('cuda') has been called (which is common in vLLM), torch.tensor() will create a GPU tensor by default, leading to performance degradation or issues during CUDA graph capture.

            self._cached_k_scale_cpu = torch.tensor(k_scale_val, dtype=torch.float32, device="cpu")

vllm/v1/attention/backends/rocm_aiter_fa.py (1532)

The scale tensor should be explicitly created on the CPU to avoid potential device-to-host synchronizations when the C++ kernel calls .item(). If torch.set_default_device('cuda') has been called, torch.tensor() will create a GPU tensor by default.

            self._cached_v_scale_cpu = torch.tensor(v_scale_val, dtype=torch.float32, device="cpu")

vllm/v1/attention/backends/rocm_attn.py (561)

The scale tensor should be explicitly created on the CPU to avoid potential device-to-host synchronizations when the C++ kernel calls .item(). If torch.set_default_device('cuda') has been called, torch.tensor() will create a GPU tensor by default.

            self._cached_k_scale_cpu = torch.tensor(k_scale_val, dtype=torch.float32, device="cpu")

vllm/v1/attention/backends/rocm_attn.py (567)

The scale tensor should be explicitly created on the CPU to avoid potential device-to-host synchronizations when the C++ kernel calls .item(). If torch.set_default_device('cuda') has been called, torch.tensor() will create a GPU tensor by default.

            self._cached_v_scale_cpu = torch.tensor(v_scale_val, dtype=torch.float32, device="cpu")

Signed-off-by: Jack Hu <Jack.Hu@amd.com>

…, in part 2 we will add back the appropriate fused custom updates Signed-off-by: Jack Hu <Jack.Hu@amd.com>

Signed-off-by: Jack Hu <Jack.Hu@amd.com>

AndreasKaratzas

This PR is clean, and test is very good, only some small nits from my end before I stamp the test.

AndreasKaratzas · 2026-06-04T17:38:00Z

+        ]
+        backend = TestBackend(*passes)
+
+        T = 5


nit: Maybe rename num tokens var

AndreasKaratzas · 2026-06-04T17:42:10Z

+        backend.check_before_ops(model.ops_in_model_before())
+        backend.check_after_ops(model.ops_in_model_after())
+
+        ATOL, RTOL = (1e-2, 1e-2)


Did you test this extensively? Any empirical atol rtol over let's say 10 reps that you could share? Maybe this threshold already exists, but if we want to be able to detect a regression, and if there is margin to tighten these, we should probably leverage it.

AndreasKaratzas · 2026-06-04T17:42:57Z

+        cache_atol = 5e-2 if is_fp8_cache else ATOL
+        cache_rtol = 1.0 if is_fp8_cache else RTOL


Same, also those tols seem high (like 1.0). Is there any explanation as to why wrt expected ULM or existing test case?

AndreasKaratzas · 2026-06-04T17:43:34Z

+@pytest.mark.parametrize("enable_aiter_triton_rope", [True, False])
+@pytest.mark.parametrize("block_size", [16])
+@pytest.mark.parametrize("dtype", [torch.bfloat16])
+@pytest.mark.parametrize("kv_cache_dtype", ["auto", "fp8"])


Is there any point in adding bf16? (I assume that auto is just half right?)

AndreasKaratzas · 2026-06-04T17:44:17Z

+@pytest.mark.parametrize("block_size", [16])
+@pytest.mark.parametrize("dtype", [torch.bfloat16])
+@pytest.mark.parametrize("kv_cache_dtype", ["auto", "fp8"])
+@pytest.mark.parametrize("rms_norm_eps", [1e-5, 1e-6])


Sorry for the potentially ignorant question, why do we need both eps vals to test?

jhu960213 added 3 commits May 13, 2026 20:16

jhu960213 requested review from BoyuanFeng, ProExpertProg, WoosukKwon, alexm-redhat, gshtras, hmellor, houseroad, mgoin, njhill, robertgshaw2-redhat, tjtanaa, tlrmchlsmth, vadiklyutiy, yewentao256, youkaichao, zhuohan123 and zou3519 as code owners May 15, 2026 14:53

mergify Bot added qwen Related to Qwen models rocm Related to AMD ROCm v1 labels May 15, 2026

github-project-automation Bot added this to AMD May 15, 2026

github-project-automation Bot moved this to Todo in AMD May 15, 2026

mergify Bot added the needs-rebase label May 15, 2026

Merge branch 'main' into jhu96/optimize-qwen30b-part1

803b694

Signed-off-by: Jack Hu <Jack.Hu@amd.com>

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jhu960213 added 3 commits May 28, 2026 16:21

Parametrized custom ops list in UT for qk norm rope kvcache

ae4a653

Signed-off-by: Jack Hu <Jack.Hu@amd.com>

Restaging ruff formatted

322b9e9

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Cleaned up more code

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jhu960213 requested a review from AndreasKaratzas as a code owner May 28, 2026 20:23

jhu960213 and others added 2 commits May 28, 2026 16:28

Merge branch 'main' into jhu96/optimize-qwen30b-part1

32406f2

Removed the no ops from ROCM_ATTN for part1 and added to unified attn…

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…, in part 2 we will add back the appropriate fused custom updates Signed-off-by: Jack Hu <Jack.Hu@amd.com>

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Comment thread tests/compile/passes/test_rocm_aiter_qk_norm_rope_kvcache_fusion.py

Added partial rotary embedding support

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zou3519 removed request for BoyuanFeng, MatthewBonanni, chaunceyjiang, hmellor, jeejeelee, orozery and zou3519 June 2, 2026 14:38

This was referenced Jun 3, 2026

[Feature][ROCm]: Add env-var gates for F2 (fused RMSNorm+MXFP4-quant) and F3 (fused RoPE+MLA KV-cache) in DeepSeek-V3 MXFP4 uplift #44440

Open

[ROCm][Compile] Fuse RMSNorm + MXFP4 quant via AITER Triton kernels (DeepSeek-R1) #44437

Draft

Added partial rotary embedding triage in qk norm rope cache unit test

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Signed-off-by: Jack Hu <Jack.Hu@amd.com>

omirosh mentioned this pull request Jun 4, 2026

[ROCm][Perf] Enable torch.compile / Inductor fusion passes on GLM-4 MTP draft #44508

Open

jhu960213 and others added 5 commits June 4, 2026 16:13

Removed comments etc

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Signed-off-by: Jack Hu <Jack.Hu@amd.com>

Renamed unit test to align with rocm aiter convention

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Signed-off-by: Jack Hu <Jack.Hu@amd.com>

Merge branch 'main' into jhu96/optimize-qwen30b-part1

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Removed some more comments

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Signed-off-by: Jack Hu <Jack.Hu@amd.com>

Some more cleanup

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[Model][Hardware][AMD]: Part 1/2 -> Enable e2e QK Norm + RoPE + KV Cache runtime fusion for Qwen3-30B-A3B on ROCM_AITER_FA, and ROCM_AITER_UNIFIED_ATTN#42749

[Model][Hardware][AMD]: Part 1/2 -> Enable e2e QK Norm + RoPE + KV Cache runtime fusion for Qwen3-30B-A3B on ROCM_AITER_FA, and ROCM_AITER_UNIFIED_ATTN#42749
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		cache_atol = 5e-2 if is_fp8_cache else ATOL
		cache_rtol = 1.0 if is_fp8_cache else RTOL

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vllm/v1/attention/backends/rocm_aiter_fa.py (1526)

vllm/v1/attention/backends/rocm_aiter_fa.py (1532)

vllm/v1/attention/backends/rocm_attn.py (561)

vllm/v1/attention/backends/rocm_attn.py (567)

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jhu960213 commented May 15, 2026 •

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