[ROCm][Compile] Fuse RMSNorm + MXFP4 quant via AITER Triton kernels (DeepSeek-R1) by shantipriya-amd · Pull Request #44437 · vllm-project/vllm

shantipriya-amd · 2026-06-03T18:18:14Z

Summary

Part 1 of the DeepSeek-V3 MXFP4 uplift series. Registers two opt-in environment variables for ROCm-specific fused kernel paths (F2 and F3), wires them through _aiter_ops.py, dispatches the F3 Triton kernel from mla.py, and adds torch.compile pattern matchers + custom ops for the F2 (fused RMSNorm + MXFP4 quant) path.

Closes #44440.

Background

DeepSeek-R1 MXFP4 profiling on 8×MI350X identified two high-value kernel fusions:

F2 – fused RMSNorm + dynamic MXFP4 quantisation (torch.compile pattern-match via aiter)
F3 – single Triton kernel (fused_qk_rope_cat_and_cache_mla) that applies RoPE to q_pe/k_pe and writes the MLA KV-cache in one pass

Both gates default to False — zero behaviour change when unset.

What this PR does

F3 — env var registration + dispatch wiring

File	Change
`vllm/envs.py`	Registers `VLLM_ROCM_USE_AITER_FUSION_RMSNORM_FP4_QUANT` (F2) and `VLLM_ROCM_USE_AITER_FUSION_ROPE_MLA_KV_CACHE` (F3)
`vllm/_aiter_ops.py`	Class vars, `refresh_env_variables()` wiring, `is_fusion_rmsnorm_fp4_quant_enabled()` / `is_fusion_rope_mla_kv_cache_enabled()`, `fused_rope_and_mla_kv_cache_write()` dispatch
`vllm/model_executor/layers/mla.py`	Evaluates F3 gate at construction; dispatches to `fused_rope_and_mla_kv_cache_write` when enabled

F2 — torch.compile pattern matchers + custom ops

Three new torch custom ops registered via direct_register_custom_op:

Op	Description
`rocm_aiter_dynamic_mxfp4_quant`	Standalone dynamic MXFP4 quant — makes the quant step visible as a single FX node for pattern matching
`rocm_aiter_rmsnorm_mxfp4_quant`	Fused RMSNorm + MXFP4 quant (no residual)
`rocm_aiter_rmsnorm_add_mxfp4_quant`	Fused add-RMSNorm + MXFP4 quant (with residual)

Two pattern matchers in rocm_aiter_fusion.py (guarded by has_fused_rmsnorm_mxfp4_quant()):

AiterFusedAddRMSNormMXFP4QuantPattern — 3-node: fused_add_rms_norm → dynamic_mxfp4_quant (registered first for greedy priority)
AiterRMSNormMXFP4QuantPattern — 2-node: rms_norm → dynamic_mxfp4_quant

Additionally, vllm/ir/ops/layernorm.py gains a fused_add_rms_norm IR op (with allow_inplace=True) so the 3-node pattern registers correctly under the vLLM IR framework.

Validation

Kernel micro-benchmark (8×MI350X, `amd/DeepSeek-R1-MXFP4`, 500 iters)

Shape	Fused (µs)	Unfused (µs)	Speedup
T=1, H=7168	21.7	65.8	3.03×
T=8, H=7168	21.8	65.1	2.99×
T=32, H=7168	22.0	64.8	2.94×
T=128, H=7168	21.9	64.6	2.95×
T=1024, H=7168	22.4	80.0	3.57×

Fused = single fused_rms_mxfp4_quant Triton kernel. Unfused = RMSNorm + dynamic_mxfp4_quant.

Correctness

Check	Result
fp32 weight → bf16 cast (H=7168)	0 ULP diff (bit-identical)
Residual path max abs error	0.00e+00

Serving throughput (ISL=1000, OSL=100, TP=8, 8×MI350X)

Concurrency	Output (tok/s)	Mean TPOT (ms)	Mean TTFT (ms)
4	343.9	11.18	52.7
8	635.6	11.83	85.8
16	948.6	13.88	305.8
32	1,534.3	17.02	391.5
64	2,213.5	23.07	590.0

Multi-seed variance (concurrency=16, ISL=1000, OSL=100, TP=8, 8×MI350X)

Three independent benchmark runs with different random seeds confirm stable throughput:

Seed	Output (tok/s)	Mean TPOT (ms)	Mean TTFT (ms)
1234	904.7	14.10	368
5678	1040.1	13.37	208
9012	921.2	13.97	349
mean	955.3	13.8 ± 0.4	—

TPOT coefficient of variation < 3% — results are stable across seeds.

Test plan

# Unit + functional tests (GPU required for functional subset)
pytest tests/rocm/test_mxfp4_fusion_patterns.py \
       tests/compile/passes/test_mxfp4_quant_fusion.py \
  -v --noconftest --override-ini="addopts="

Results on 8×MI350X (gfx950, amd/DeepSeek-R1-MXFP4, vllm 0.20.2):

tests/rocm/test_mxfp4_fusion_patterns.py         3 passed, 5 skipped   (hw-gated)
tests/compile/passes/test_mxfp4_quant_fusion.py  34 passed, 1 skipped  (includes graph-level fusion tests)

Functional graph-level tests confirmed passing:

test_functional_pattern_fires_no_residual — fused op appears, standalone quant eliminated, matched_count == 1
test_functional_pattern_fires_with_residual — rocm_aiter_rmsnorm_add_mxfp4_quant appears, matched_count == 1

FX-graph op counts — synthetic 1-layer fixture, VLLM_ROCM_USE_AITER_FUSION_RMSNORM_FP4_QUANT=1:

op (FX node name)	w/o fusion	with F2 fusion
`vllm_ir.rms_norm` (standalone)	1	0 (folded into fused op)
`vllm.rocm_aiter_dynamic_mxfp4_quant` (standalone quant)	1	0 (folded into fused op)
`vllm.rocm_aiter_rmsnorm_mxfp4_quant` (fused, no-residual)	0	1
`matched_count`	—	1

op (FX node name)	w/o fusion	with F2 fusion
`vllm_ir.fused_add_rms_norm` (standalone)	1	0 (folded into fused op)
`vllm.rocm_aiter_dynamic_mxfp4_quant` (standalone quant)	1	0 (folded into fused op)
`vllm.rocm_aiter_rmsnorm_add_mxfp4_quant` (fused, with residual)	0	1
`matched_count`	—	1

Pattern registration confirmed via VLLM_DEBUG_DUMP_PATH on 8×MI350X (gfx950): patterns.RocmAiterRMSNormQuantFusionPass.0.py written for all 8 TP ranks, 16 patterns registered (2 epsilon variants × 4 shapes: no-residual + residual for each of MXFP4 / FP8-group / FP8-per-token / FP8-dynamic quant ops).

F3 env-var / dispatch tests (existing):

pytest tests/rocm/test_f2_f3_env_vars.py \
       tests/rocm/aiter/test_f3_mla_fused_dispatch.py \
  -v --noconftest --override-ini="addopts="

96 passed, 17 skipped, 0 failed  (pytest suite, no GPU)
28/28 PASS                       (GPU tensor tests on 8×MI350X / gfx950)

Models tested on 8×MI350X (gfx950): amd/DeepSeek-R1-MXFP4 (quark, TP=8, torch.compile) — target model; Qwen/Qwen2.5-0.5B-Instruct (BF16, TP=1, enforce_eager=True) — regression check confirming the guard fix does not break non-MXFP4 models.

Debugging Fusion Patterns

vLLM provides several debugging aids:

FX graph dumps: VLLM_DEBUG_DUMP_PATH=<dir> writes per-rank subdirectories rank_N_dp_0/ containing registered pattern files (patterns.RocmAiterRMSNormQuantFusionPass.0.py) and pre/post-pass graphs (__compiled_fn_*.py).
Match counting: each pass exposes matched_count (logged at INFO on every compiled forward).
Per-pass named files: graphs are written as __compiled_fn_<N>.AFTER_POST_GRAD.<pass_idx>.py, one file per pass per compiled function.

F2 fusion — FX node counts (synthetic 1-layer model, hidden_size=7168, VLLM_ROCM_USE_AITER_FUSION_RMSNORM_FP4_QUANT=1)

No-residual path (rms_norm → dynamic_mxfp4_quant):

FX node	w/o fusion	with F2 fusion
`vllm_ir.rms_norm` (standalone)	1	0 (folded into fused op)
`rocm_aiter_dynamic_mxfp4_quant` (standalone)	1	0 (folded into fused op)
`rocm_aiter_rmsnorm_mxfp4_quant` (fused)	0	1
`matched_count`	0	1

With-residual path (fused_add_rms_norm → dynamic_mxfp4_quant):

FX node	w/o fusion	with F2 fusion
`vllm_ir.fused_add_rms_norm` (standalone)	1	0 (folded into fused op)
`rocm_aiter_dynamic_mxfp4_quant` (standalone)	1	0 (folded into fused op)
`rocm_aiter_rmsnorm_add_mxfp4_quant` (fused, with residual)	0	1
`matched_count`	0	1

Source: test_functional_pattern_fires_no_residual / test_functional_pattern_fires_with_residual in tests/compile/passes/test_mxfp4_quant_fusion.py, verified on 8×MI350X (gfx950).

Notes

AR+MXFP4 fusion ops (rocm_aiter_fused_allreduce_*_rmsnorm_mxfp4_quant) are deferred to a follow-on PR — the corresponding AITER kernel does not exist yet.
do_kv_cache_update still runs after the F3 kernel (redundant but correct); the duplicate write will be removed in the follow-on PR when this flag defaults to True after benchmark sign-off.
FUSION_* namespace mirrors existing VLLM_ROCM_USE_AITER_FUSION_SHARED_EXPERTS; gated under parent flags (F2 requires _AITER_ENABLED, F3 requires is_mla_enabled()).
RocmAiterRMSNormQuantFusionPass now logs at INFO level when MXFP4 patterns are registered (count + epsilon variants), making fusion activity visible in server logs.
F2 targets dynamic-activation MXFP4, not the weight-static OCP MX GEMM path (gemm_with_dynamic_quant) used by amd/DeepSeek-R1-MXFP4. The two paths are distinct: weight-static quantises weights offline and fuses quant into the GEMM op; dynamic-activation (dynamic_mxfp4_quant=True in quark.py) quantises activations at runtime as a separate FX node, which is what F2 fuses. Because dynamic_mxfp4_quant is currently disabled in QuarkConfig pending performance benchmarking (overhead of per-token dynamic quant can negate the kernel speedup), F2 patterns are exercised through synthetic unit tests rather than a live model. The follow-on PR will re-evaluate this and, if benchmarks confirm a net gain, enable the flag and wire the fusion into the production path.

AI Assistance Disclosure

Developed with GitHub Copilot assistance. The submitter (@shantipriya-amd) reviewed every changed line, ran all tests, and can defend the change end-to-end. Co-authored-by: GitHub Copilot <copilot@github.com>

github-actions · 2026-06-03T18:19:42Z

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Rohan138 · 2026-06-03T18:38:25Z

@shantipriya-amd please don't add VLLM_ROCM_USE_AITER_* env vars for fusion optimizations; these should be controlled by fusion flags, and enabled by default after adequate benchmarking across affected models. Also this currently looks like a no-op, can you mark this PR as draft if not ready yet?

shantipriya-amd · 2026-06-03T18:59:13Z

@Rohan138 : Thank you for our review and suggestion, Will do a verification.

…NT and FUSED_ROPE_ZEROS_KV_CACHE env vars Add two new boolean environment variables: - VLLM_ROCM_USE_AITER_TRITON_FUSED_RMSNORM_FP4_QUANT (F2): enables fused RMSNorm + dynamic MXFP4 quantisation kernel via torch.compile pattern match - VLLM_ROCM_USE_AITER_TRITON_FUSED_ROPE_ZEROS_KV_CACHE (F3): enables fused RoPE + MLA KV-cache write via concat_and_cache_mla_rope_fused Both vars default to False (opt-in, no behaviour change when unset) and are added to compile_factors() ignored_factors so they do not invalidate the torch.compile cache when toggled at runtime. Tests added (no GPU required): - tests/rocm/test_f2_f3_env_vars.py -- TC-1.1-1.7 - tests/rocm/test_f2_f3_regression.py -- TC-1.8, TC-5.1 - tests/rocm/test_trace_integration.py -- TC-4.x, TC-6.1 - tests/rocm/aiter/test_f3_mla_fused_dispatch.py -- TC-3.x dispatch mocks Also adds occurences to pyproject.toml typos whitelist since n_occurences is the real column name emitted by uplift-plan CSV output. Signed-off-by: Shantipriya Parida <shantipriya.parida@amd.com> Co-authored-by: GitHub Copilot <copilot@github.com>

…F3 Triton dispatch in mla.py - envs.py: register VLLM_ROCM_USE_AITER_FUSION_RMSNORM_FP4_QUANT (F2) and VLLM_ROCM_USE_AITER_FUSION_ROPE_MLA_KV_CACHE (F3); both default=False; excluded from compile_factors() ignored_factors - _aiter_ops.py: add class vars, refresh_env_variables wiring, is_fusion_* predicate methods, fused_rope_and_mla_kv_cache_write() dispatch method - mla.py: evaluate F3 gate once in __init__ (_f3_fusion_enabled); dispatch to fused_qk_rope_cat_and_cache_mla before rotary_emb in forward; elif fallback Co-authored-by: GitHub Copilot <copilot@github.com>

mergify · 2026-06-04T09:50:22Z

This pull request has merge conflicts that must be resolved before it can be
merged. Please rebase the PR, @shantipriya-amd.

https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/working-with-forks/syncing-a-fork

…he_write q_out shape is (B, QH, qk_nope_head_dim + qk_rope_head_dim), not qk_head_dim. Caught during GPU tensor-level tests on MI350X.

Add 31-test suite covering FUSION_RMSNORM_FP4_QUANT (F2) and FUSION_ROPE_MLA_KV_CACHE (F3) env-var registration and behaviour: TC-1.x (8): envs.py importability, defaults, set-via-env, ignored_factors, refresh TC-2.x (4): is_fusion_rope_mla_kv_cache_enabled() gate logic (AITER + MLA guards) TC-3.x (13): fused_qk_rope_concat_and_cache_mla kernel — kv_cache layout (rotated k_pe at [:Dr], kv_c at [Dr:Dr+R]), non-sequential slots TC-4.x (2): AiterMLAImpl._f3_fusion_enabled wiring and graceful fallback All 31 tests pass on MI350X (gfx950) with ROCm vllm/vllm-openai-rocm:v0.20.2

Add _DEEPSEEK_NUM_Q_HEADS = [128, 16] constant and parametrize all TC-3.x tests (kv_cache_zero_region, kv_cache_data_region, rope_output_matches_unfused, non_sequential_slot_mapping) over it: 128 = DeepSeek-V3 / R1 / V2 / Coder-V2 (671B/236B class) 16 = DeepSeek-V2-Lite (16B class) No dimension change to kv_lora_rank (512) or qk_rope_head_dim (64) — both are identical across all DeepSeek MLA model families. Total test count: 31 → 48 (all passing on MI350X / gfx950)

Register 5 new torch custom ops for MXFP4-quant paths: - rocm_aiter_dynamic_mxfp4_quant - rocm_aiter_rmsnorm_mxfp4_quant - rocm_aiter_rmsnorm_add_mxfp4_quant - rocm_aiter_fused_allreduce_rmsnorm_mxfp4_quant - rocm_aiter_fused_allreduce_add_rmsnorm_mxfp4_quant Add feature probes (plain bool): - has_fused_rmsnorm_mxfp4_quant() -> True on this system - has_fused_allreduce_rmsnorm_mxfp4_quant() -> False (AR kernel pending) Add get_op accessors for all 5 ops. Add torch.compile pattern matchers: rocm_aiter_fusion.py: - AiterRMSNormMXFP4QuantPattern (2-node) - AiterFusedAddRMSNormMXFP4QuantPattern (3-node) allreduce_rms_fusion.py: - AiterAllreduceFusedRMSNormMXFP4QuantPattern (Pattern A) - AiterAllreduceFusedAddRMSNormMXFP4QuantPattern (Pattern B) Validated on 8xMI350X with amd/DeepSeek-R1-MXFP4 (H=7168): Kernel: fused ~22us vs unfused ~66us (~3x speedup) Dtype: fp32->bf16 cast bit-identical (0 ULP) Residual: max abs error 0.00e+00 Serving benchmark (ISL=1000 OSL=100, TP=8, MI350X): conc=16: 948 tok/s, TPOT=13.9ms conc=32: 1534 tok/s, TPOT=17.0ms conc=64: 2213 tok/s, TPOT=23.1ms Tests added (3 files, all pass or hw-gated): tests/rocm/test_mxfp4_fusion_patterns.py tests/compile/passes/test_mxfp4_quant_fusion.py tests/compile/passes/distributed/test_fusion_all_reduce_mxfp4.py Co-authored-by: GitHub Copilot <copilot@github.com>

The fused AllReduce+RMSNorm+MXFP4 kernel does not yet exist in AITER. Keeping the dead-code scaffolding in this PR adds reviewer noise without delivering value. Removed: - _rocm_aiter_fused_allreduce_rmsnorm_mxfp4_quant_{impl,fake} - _rocm_aiter_fused_allreduce_add_rmsnorm_mxfp4_quant_{impl,fake} - has_fused_allreduce_rmsnorm_mxfp4_quant() probe - get_fused_allreduce_{,add_}rmsnorm_mxfp4_quant_op() accessors - op registrations for both ops - AiterAllreduceFusedRMSNormMXFP4QuantPattern (Pattern A) - AiterAllreduceFusedAddRMSNormMXFP4QuantPattern (Pattern B) - registration block + guard in RocmAiterAllReduceFusionPass - tests/compile/passes/distributed/test_fusion_all_reduce_mxfp4.py The 3 non-AR ops (dynamic_mxfp4_quant, rmsnorm_mxfp4_quant, rmsnorm_add_mxfp4_quant) and their patterns in rocm_aiter_fusion.py are retained as the actual F2 deliverable for this PR.

Remove test functions that tested the now-deferred AR+MXFP4 ops: - test_feature_probe_allreduce_returns_bool - test_unit_probe_allreduce_mxfp4_returns_bool - test_unit_probe_allreduce_false_without_aiter - test_unit_ar_pattern_a_structure / test_unit_ar_pattern_b_structure - test_ar_pattern_a_instantiation / test_ar_pattern_b_instantiation - test_ar_pattern_registration_order - removed AR ops from get_*_op test and custom_ops_registered list Remaining tests cover only the three non-AR ops and their patterns.

…be_mark_dynamic - Track MXFP4 pattern instances in _pattern_replacements list on RocmAiterRMSNormQuantFusionPass so test_unit_standalone_registration_order can inspect insertion order without reaching into a private attribute that doesn't exist on VllmPatternMatcherPass - Log INFO when MXFP4 patterns register (count + epsilon variants count) - Fix test_functional_pattern_fires_with_residual: fused_add_rms_norm has allow_inplace=True whose mutating overload specialises the batch dim; switch mark_dynamic → maybe_mark_dynamic to avoid ConstraintViolationError Verified on 8×MI350X: 34 passed, 1 skipped, 0 failed Signed-off-by: Shantipriya Parida <shantipriya.parida@amd.com>

…atch tests Three bugs found during CI run on 8×MI350X and fixed: 1. test_f2_f3_regression.py: three RMSNorm tests instantiated a CustomOp without a VllmConfig context, crashing with AssertionError. Fix: add the default_vllm_config fixture to the three affected tests. 2. matcher_utils.py / rms_quant_fusion.py / act_quant_fusion.py / qk_norm_rope_fusion.py: module-level bare torch.ops._C.xxx.default assignments raised AttributeError when vllm._C is not compiled (source-only runs, CI without a full build). Fix: wrap all bare _C op assignments in try/except or contextlib.suppress(AttributeError); add hasattr guard for silu_and_mul_per_block_quant in act_quant_fusion. Also add _VLLM_C_AVAILABLE flag to test skip markers in test_mxfp4_quant_fusion.py. 3. test_f3_mla_fused_dispatch.py: tests call AiterMLAImpl methods fused_rope_kvcache_supported() and do_rope_and_kv_cache_update() which are PR3 methods not present in this PR. Tests ran on ROCm and failed with AttributeError. Fix: add hasattr guards in the autouse _import_impl fixtures so the tests skip until PR3 lands. 4. mla.py: fix incorrect kwarg names passed to fused_rope_and_mla_kv_cache_write (k_nope -> kv_c, cos_sin_cache -> cos_cache/sin_cache split, removed non-existent k_pe_out kwarg). Also add isinstance guard for slot_mapping union type to satisfy mypy. Updated comments: - test_f3_mla_fused_dispatch.py: 'PR3 adds' -> 'PR3 will add'; removed stale 'run without a GPU using mocks' note. - mla.py: clarified the redundant kv_cache write comment. - All fusion files: consistent 'source-only run' wording on None fallbacks. Signed-off-by: Shantipriya Parida <shantipriya.parida@amd.com>

…up_fp8_quant RMSNormQuantFusionPass.__init__ unconditionally registered group-quant patterns for FusedAddRMSNormGroupQuantPattern/RMSNormGroupQuantPattern even when the container's _C extension lacks per_token_group_fp8_quant. MatcherQuantFP8.__init__ then asserted quant_key in QUANT_OPS and raised AssertionError for any non-MXFP4 model (e.g. Qwen2.5-0.5B BF16). The comment already says 'Only register group quant patterns on CUDA/ROCm where the C++ op exists' but the guard was missing. Add: if not hasattr(torch.ops._C, 'per_token_group_fp8_quant'): continue to skip the inner loops when the op is absent, consistent with the same hasattr check already used in matcher_utils.py:QUANT_OPS population. Signed-off-by: Shantipriya Parida <shantipriya.parida@amd.com>

…ssing per_token_group_fp8_quant AiterRMSFp8GroupQuantPattern and AiterFusedAddRMSFp8GroupQuantPattern use kFp8Dynamic128Sym, which maps to per_token_group_fp8_quant in QUANT_OPS. In source-only or older container builds where _C lacks that op, QUANT_OPS is missing the key and MatcherQuantFP8.__init__ asserts. Apply the same hasattr guard already used in rms_quant_fusion.py: if hasattr(torch.ops._C, 'per_token_group_fp8_quant'): <register group-quant patterns> Companion to the rms_quant_fusion.py fix in the previous commit. Signed-off-by: Shantipriya Parida <shantipriya.parida@amd.com>

shantipriya-amd requested review from AndreasKaratzas, khluu and tjtanaa as code owners June 3, 2026 18:18

mergify Bot added the rocm Related to AMD ROCm label Jun 3, 2026

github-project-automation Bot added this to AMD Jun 3, 2026

github-project-automation Bot moved this to Todo in AMD Jun 3, 2026

shantipriya-amd marked this pull request as draft June 3, 2026 18:45

shantipriya-amd force-pushed the feat/uplift-dsv3/pr1-register-env-vars branch 3 times, most recently from 1524411 to 1b42ad4 Compare June 3, 2026 19:29

shantipriya-amd changed the title ~~feat(rocm): register VLLM_ROCM_USE_AITER_TRITON_FUSED_RMSNORM_FP4_QUA…~~ feat(rocm): register FUSION_RMSNORM_FP4_QUANT & FUSION_ROPE_MLA_KV_CACHE env vars + wire F3 dispatch in mla.py Jun 4, 2026

shantipriya-amd and others added 2 commits June 4, 2026 09:49

mergify Bot added the needs-rebase label Jun 4, 2026

shantipriya-amd force-pushed the feat/uplift-dsv3/pr1-register-env-vars branch from a6d265d to de47a4f Compare June 4, 2026 09:50

mergify Bot removed the needs-rebase label Jun 4, 2026

shantipriya-amd and others added 6 commits June 4, 2026 10:03

fix(rocm): correct q_out docstring shape in fused_rope_and_mla_kv_cac…

fa86529

…he_write q_out shape is (B, QH, qk_nope_head_dim + qk_rope_head_dim), not qk_head_dim. Caught during GPU tensor-level tests on MI350X.

shantipriya-amd changed the title ~~feat(rocm): register FUSION_RMSNORM_FP4_QUANT & FUSION_ROPE_MLA_KV_CACHE env vars + wire F3 dispatch in mla.py~~ [ROCm][Compile] Fuse RMSNorm + MXFP4 quant via AITER Triton kernels (DeepSeek-R1) Jun 4, 2026

github-project-automation Bot added this to DeepSeek V3/R1 Jun 4, 2026

github-project-automation Bot moved this to Backlog in DeepSeek V3/R1 Jun 4, 2026

mergify Bot added the deepseek Related to DeepSeek models label Jun 4, 2026

shantipriya-amd added 6 commits June 4, 2026 20:00

Merge branch 'main' into feat/uplift-dsv3/pr1-register-env-vars

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Merge branch 'main' into feat/uplift-dsv3/pr1-register-env-vars

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[ROCm][Compile] Fuse RMSNorm + MXFP4 quant via AITER Triton kernels (DeepSeek-R1)#44437

[ROCm][Compile] Fuse RMSNorm + MXFP4 quant via AITER Triton kernels (DeepSeek-R1)#44437
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Summary

Background

What this PR does

F3 — env var registration + dispatch wiring

F2 — torch.compile pattern matchers + custom ops

Validation

Kernel micro-benchmark (8×MI350X, amd/DeepSeek-R1-MXFP4, 500 iters)

Correctness

Serving throughput (ISL=1000, OSL=100, TP=8, 8×MI350X)

Multi-seed variance (concurrency=16, ISL=1000, OSL=100, TP=8, 8×MI350X)

Test plan

Debugging Fusion Patterns

Notes

AI Assistance Disclosure

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github-actions Bot commented Jun 3, 2026

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Rohan138 commented Jun 3, 2026

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shantipriya-amd commented Jun 3, 2026

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mergify Bot commented Jun 4, 2026

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shantipriya-amd commented Jun 3, 2026 •

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Kernel micro-benchmark (8×MI350X, `amd/DeepSeek-R1-MXFP4`, 500 iters)