[ROCm] DeepSeekV4-Flash-Base model enablement on ROCm with triton & torchfallback#41136
[ROCm] DeepSeekV4-Flash-Base model enablement on ROCm with triton & torchfallback#41136lcskrishna wants to merge 13 commits into
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Hi @lcskrishna, thanks for the contribution! We tried validating this PR on our ROCm setup (MI350X8) with DeepSeek-V4-Flash-Base FP8, and would like to share our observations. Environment
Observations (TP=1)
From our debugging, the issue seems to occur in the ROCm attention fallback path (around Additional debugging
This suggests the issue might be in the multi-token decode path rather than prefill. TP=8
Could you help clarify the following so we can better align environments?
This will help us determine whether this is an environment mismatch or a missing ROCm fallback path. Thanks! |
Merge upstream changes and re-evaluate changes.
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@tjtanaa the PR is rebased to main branch and removed unnecessary fallbacks. The code has been re-evaluated and tested as per the description for DeepSeekV4-Flash-Base on MI300 & MI350 with all the smoke tests (various CURL commands) & GSM8K matching. Below are the results. GSM8K Results:
One thing I would like to highlight is - the C++ extension - fused_deepseek_v4_qnorm_rope_kv_rope_quant_insert produces garbage results at the moment and also doesn't work on MI300 due to some issues and requires some re-work. For now, the fallback for this kernel is still added and kept under the env variable scope. |
Resolved two conflicts in vllm/model_executor/layers/deepseek_v4_attention.py:
* Decode path: dropped the
``VLLM_ROCM_USE_V4_TRITON_FALLBACK``-gated ``rocm_forward_decode_fallback``
branch — upstream unified the call to ``flash_mla_with_kvcache`` for
both CUDA and ROCm. The ROCm path is already routed to our
``flash_mla_with_kvcache_rocm`` Triton kernel via
``vllm.v1.attention.ops.flashmla`` (which already accepts the new
``is_fp8_kvcache``/``extra_k_cache``/``extra_indices_in_kvcache``
kwargs).
* Prefill path: dropped the env-gated branch around
``flash_mla_sparse_fwd`` and adopted upstream's signature (no longer
returns a 3-tuple). Our ``flash_mla_sparse_fwd_rocm`` writes via
``out=`` so the return value is harmless to ignore.
Post-merge cleanup:
* vllm/platforms/rocm.py: removed our duplicate "deepseek_v4_fp8"
entry — upstream now adds it as the first member of
``supported_quantization``.
* vllm/envs.py: trimmed the ``VLLM_ROCM_USE_V4_TRITON_FALLBACK``
docstring from four call sites down to two (SWA K-cache writer and
sparse indexer). The MLA decode / sparse-prefill paths are now
permanently routed through the ROCm Triton fallbacks via flashmla.py
on ROCm — no env-var toggle needed there any more.
Kept (still required after the merge):
* vllm/model_executor/layers/sparse_attn_indexer.py — dispatch to
``rocm_sparse_attn_indexer_no_insert`` when
skip_k_cache_insert + AITER disabled + env-var on.
* vllm/v1/attention/ops/rocm_sparse_attn_indexer.py (recovered
pre-rebase orchestration).
* vllm/v1/attention/ops/rocm_flash_mla_sparse.py +
flashmla.py ROCm dispatch.
* vllm/model_executor/models/deepseek_v4.py:
``_resolve_deepseek_v4_expert_dtype`` — still required because
upstream's new cached property only honours an explicit
``hf_config.expert_dtype`` and otherwise defaults to ``"fp4"``,
misrouting FP8 checkpoints that ship without the field.
* The Python SWA K-cache writer reference + env-gate around the
HIPified ``fused_deepseek_v4_qnorm_rope_kv_rope_quant_insert``
C++ kernel (still buggy on MI300X / FNUZ).
Backup tag: pre-upstream-merge-0512.
Co-authored-by: Cursor <cursoragent@cursor.com>
Upstream-added ``mhc_fused_post_pre`` calls three tilelang kernels (``mhc_fused_tilelang``, ``mhc_post_tilelang``, ``mhc_pre_big_fuse_tilelang``) that all use Program Dependent Launch (PDL — Hopper-only). On ROCm tilelang's ``MarkCudaSyncCalls`` raises ``PDL is not supported`` at JIT-compile time, taking down every TP worker during profile_run: [TileLang:...]: TileLang begins to compile kernel `mhc_post_tilelang` tvm.error.InternalError: Check failed: ... PDL is not supported The non-fused ``mhc_pre`` and ``mhc_post`` already carry torch ROCm fallbacks; this commit composes them to back the fused op on ROCm, matching the contract (4-tuple of residual_cur / post_mix_cur / comb_mix_cur / layer_input_cur with the exact same shapes and dtypes as the tilelang path). The CUDA path is untouched. This unblocks DSv4-Flash-Base-FP8 profile_run on MI300X after the upstream merge that wired the fused op into the layer forward path. Co-authored-by: Cursor <cursoragent@cursor.com>
Merge upstream and validate
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We have landed triton sparse mla backend for dsv4 #41812 , and will land a aiter mhc PR #41946 that bugfix the dsv4 code path, remove the tilelang dependencies. Can you help to check by then what we need to do to enable for DeepSeekV4-Flash-Base? Moreover, we do not want to introduce more flags e.g. |
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Thanks @tjtanaa for providing an update on #41812 and #41946 - I believe I can drop the env variable once the PRs are merged. The following might be still needed though:
Could you please share rough timeline of merging the #41946 which I can re-base and re-evaluate. Please let me know your thoughts. |
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FP8 Check point fixes - More robust way of using expert_dtype: #42970 |
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This pull request has merge conflicts that must be resolved before it can be |
Enable the DeepSeek V4 model setup to create the same three attention auxiliary streams on ROCm that CUDA already uses. This activates the existing decode overlap choreography for CSA: c4a layers can overlap the indexer pipeline, main KV compression, and SWA insertion, while c128a layers can overlap main KV compression with SWA insertion. XPU keeps the existing serial fallback, and CUDA behavior remains unchanged. Duplicate-work check: issue vllm-project#41820 remains open; unauthenticated GitHub API searches found no open PR with "41820 in:body" and the closest open PRs from area keyword searches were vllm-project#41136 and vllm-project#41834, which cover ROCm enablement/fallbacks and NVIDIA SM12x support rather than this ROCm aux-stream gate. Tests: .venv/bin/python -m pytest tests/models/test_deepseek_v4_rocm_multistream.py -q (3 passed, 16 warnings); pre-commit run ruff-check --files vllm/models/deepseek_v4/nvidia/model.py tests/models/test_deepseek_v4_rocm_multistream.py (passed); pre-commit run ruff-format --files vllm/models/deepseek_v4/nvidia/model.py tests/models/test_deepseek_v4_rocm_multistream.py (passed). AI assistance was used for implementation and validation.
Enable the DeepSeek V4 model setup to create the same three attention auxiliary streams on ROCm that CUDA already uses. This activates the existing decode overlap choreography for CSA: c4a layers can overlap the indexer pipeline, main KV compression, and SWA insertion, while c128a layers can overlap main KV compression with SWA insertion. XPU keeps the existing serial fallback, and CUDA behavior remains unchanged. Duplicate-work check: issue vllm-project#41820 remains open; unauthenticated GitHub API searches found no open PR with "41820 in:body" and the closest open PRs from area keyword searches were vllm-project#41136 and vllm-project#41834, which cover ROCm enablement/fallbacks and NVIDIA SM12x support rather than this ROCm aux-stream gate. Tests: .venv/bin/python -m pytest tests/models/test_deepseek_v4_rocm_multistream.py -q (3 passed, 16 warnings); pre-commit run ruff-check --files vllm/models/deepseek_v4/nvidia/model.py tests/models/test_deepseek_v4_rocm_multistream.py (passed); pre-commit run ruff-format --files vllm/models/deepseek_v4/nvidia/model.py tests/models/test_deepseek_v4_rocm_multistream.py (passed). AI assistance was used for implementation and validation. Signed-off-by: vLLM Contributor <contributor@vllm.ai>
Enable the DeepSeek V4 model setup to create the same three attention auxiliary streams on ROCm that CUDA already uses. This activates the existing decode overlap choreography for CSA: c4a layers can overlap the indexer pipeline, main KV compression, and SWA insertion, while c128a layers can overlap main KV compression with SWA insertion. XPU keeps the existing serial fallback, and CUDA behavior remains unchanged. Duplicate-work check: issue vllm-project#41820 remains open; unauthenticated GitHub API searches found no open PR with "41820 in:body" and the closest open PRs from area keyword searches were vllm-project#41136 and vllm-project#41834, which cover ROCm enablement/fallbacks and NVIDIA SM12x support rather than this ROCm aux-stream gate. Tests: .venv/bin/python -m pytest tests/models/test_deepseek_v4_rocm_multistream.py -q (3 passed, 16 warnings); pre-commit run ruff-check --files vllm/models/deepseek_v4/nvidia/model.py tests/models/test_deepseek_v4_rocm_multistream.py (passed); pre-commit run ruff-format --files vllm/models/deepseek_v4/nvidia/model.py tests/models/test_deepseek_v4_rocm_multistream.py (passed). AI assistance was used for implementation and validation. Signed-off-by: vLLM Contributor <contributor@vllm.ai>
Purpose
This PR enables to run DeepSeekV4-Flash-Base model (FP8) on ROCm with triton & torch fallbacks. The following major changes have been performed:
Test Plan
Test Result
Server command
Curl commands & results
GSM8K Results
Result
2026-05-06:11:36:32 INFO [loggers.evaluation_tracker:119] Saving per-task samples to eval_results/gsm8k_20260506_105215/datasets__DeepSeek-V4-Flash-Base/*.jsonl
local-completions ({'model': '/datasets/DeepSeek-V4-Flash-Base/', 'base_url': 'http://0.0.0.0:8000/v1/completions', 'num_concurrent': 64, 'max_retries': 3, 'tokenized_requests': False, 'tokenizer_backend': None, 'max_gen_toks': 1024}), gen_kwargs: ({}), limit: None, num_fewshot: 5, batch_size: auto
SUCCESS. Results in ./eval_results/gsm8k_20260506_105215
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