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[ROCm] DeepSeekV4-Flash-Base model enablement on ROCm with triton & torchfallback#41136

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[ROCm] DeepSeekV4-Flash-Base model enablement on ROCm with triton & torchfallback#41136
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@lcskrishna lcskrishna commented Apr 28, 2026

Purpose

This PR enables to run DeepSeekV4-Flash-Base model (FP8) on ROCm with triton & torch fallbacks. The following major changes have been performed:

  • Quantization whitelist of deepseek_v4_fp8 (registration)
  • Fp8 MoE Experts (Supports only experts_dtype=FP8 for now)
  • MHC - The current implementation uses TileLang Kernels. This PR enables a fallback to torch naive implementation, the TileLang / equivalent will be enabled in further PRs.
  • FP8 blockscale Einsum - created a fallback of torch dequant & torch.einsum fallback instead of using in deep_gemm
  • TopK Softplus SQRT (CUDA) function - this fallsback to a naive torch softplus + topk + renorm.
  • Router GEMM BF16 FP32 - currently fallsback to torch.linear
  • Sparse Attention Indexer - (Skip Insert) - Custom Op rocm_sparse_attn_indexer_no_insert
  • Flash MLA sparse fwd/decode - Created a temporary fallback rocm_flash_mla_sparse.py with Triton kernels.

Test Plan

Test Result

Server command

MODEL_DIR=/models/DSV4-Flash-Base
## clone from https://huggingface.co/deepseek-ai/DeepSeek-V4-Flash-Base

export VLLM_ENGINE_READY_TIMEOUT_S=3600
export VLLM_MEMORY_PROFILER_ESTIMATE_CUDAGRAPHS=0

vllm serve ${MODEL_DIR} \
  --trust-remote-code \
  --kv-cache-dtype fp8 \
  --max-model-len 800000 \
  --gpu-memory-utilization 0.95 \
  --tensor-parallel-size 8 \
  --max-num-seqs 512 \
  --max-num-batched-tokens 512 \
  --tokenizer-mode deepseek_v4 \
  --tool-call-parser deepseek_v4 \
  --enable-auto-tool-choice \
  --reasoning-parser deepseek_v4 \
  --enforce-eager \
  --kernel-config '{"moe_backend":"triton"}' \
  "${EXTRA_ARGS[@]}"

Curl commands & results

curl -sS -X POST http://localhost:8000/v1/completions   -H 'Content-Type: application/json'   -d "{
    \"model\": \"$MODEL\",
    \"prompt\": \"The capital of France is\",
    \"max_tokens\": 8,
    \"temperature\": 0
  }" | python3 -m json.tool
curl -s http://0.0.0.0:8000/v1/completions   -H 'Content-Type: application/json'   -d '{"model":"/shared_inference/models_blog/DeepSeek-V4-Flash-
       "prompt":"Q: 17 * 23 = \nA:", "max_tokens":12, "temperature":0}'   | jq -r '.choices[0].text'

GSM8K Results

lm_eval --model local-completions \
    --tasks gsm8k \
    --model_args model=/models/DeepSeek-V4-Flash-FP8/,base_url=http://localhost:8000/v1/completions,num_concurrent=64,max_retries=3,tokenized_requests=False 

Result

2026-05-06:11:36:32 INFO [loggers.evaluation_tracker:119] Saving per-task samples to eval_results/gsm8k_20260506_105215/datasets__DeepSeek-V4-Flash-Base/*.jsonl
local-completions ({'model': '/datasets/DeepSeek-V4-Flash-Base/', 'base_url': 'http://0.0.0.0:8000/v1/completions', 'num_concurrent': 64, 'max_retries': 3, 'tokenized_requests': False, 'tokenizer_backend': None, 'max_gen_toks': 1024}), gen_kwargs: ({}), limit: None, num_fewshot: 5, batch_size: auto

Tasks Version Filter n-shot Metric Value Stderr
gsm8k 3 flexible-extract 5 exact_match 0.9242 ± 0.0073
strict-match 5 exact_match 0.9249 ± 0.0073

SUCCESS. Results in ./eval_results/gsm8k_20260506_105215


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  • The purpose of the PR, such as "Fix some issue (link existing issues this PR will resolve)".
  • The test plan, such as providing test command.
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  • (Optional) The necessary documentation update, such as updating supported_models.md and examples for a new model.

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@mergify mergify Bot added deepseek Related to DeepSeek models rocm Related to AMD ROCm v1 labels Apr 28, 2026
@github-project-automation github-project-automation Bot moved this to Todo in AMD Apr 28, 2026
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zihaomu commented Apr 29, 2026

Hi @lcskrishna, thanks for the contribution!

We tried validating this PR on our ROCm setup (MI350X8) with DeepSeek-V4-Flash-Base FP8, and would like to share our observations.

Environment

  • GPU: MI350X8
  • Model: DeepSeek-V4-Flash-Base (FP8)

Observations (TP=1)

  • The PR builds successfully and the server can start
  • /health endpoint works as expected
  • However, /v1/completions does not complete under normal execution

From our debugging, the issue seems to occur in the ROCm attention fallback path (around rocm_flash_mla_sparse.py), specifically near q.to(torch.float32), where we hit hipErrorIllegalState.

Additional debugging

  • If we bypass the compressed aux/indexer path and force SWA-only prefill:
    • max_tokens=1 can return (e.g., " Paris")
    • max_tokens > 1 still triggers a GPU memory access fault during decode

This suggests the issue might be in the multi-token decode path rather than prefill.

TP=8

  • In our setup, TP=8 is currently blocked earlier during initialization due to RCCL/PyNccl all-reduce issues, so we have not yet been able to validate generation in TP=8.

Could you help clarify the following so we can better align environments?

  1. GPU model and ROCm version used for validation
  2. PyTorch / Triton / vLLM versions
  3. Whether validation was done with TP=1 or TP=8
  4. The exact server launch command and required env variables
  5. Whether rocm_flash_mla_sparse.py has been tested for multi-token decode

This will help us determine whether this is an environment mismatch or a missing ROCm fallback path.

Thanks!

@mergify mergify Bot removed the needs-rebase label May 7, 2026
@lcskrishna
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lcskrishna commented May 7, 2026

@tjtanaa the PR is rebased to main branch and removed unnecessary fallbacks. The code has been re-evaluated and tested as per the description for DeepSeekV4-Flash-Base on MI300 & MI350 with all the smoke tests (various CURL commands) & GSM8K matching. Below are the results.

GSM8K Results:

Tasks Version Filter n-shot Metric Value Stderr
gsm8k 3 flexible-extract 5 exact_match 0.9234 ± 0.0073
strict-match 5 exact_match 0.9242 ± 0.0073

One thing I would like to highlight is - the C++ extension - fused_deepseek_v4_qnorm_rope_kv_rope_quant_insert produces garbage results at the moment and also doesn't work on MI300 due to some issues and requires some re-work. For now, the fallback for this kernel is still added and kept under the env variable scope.

cc: @wuhuikx @amathews-amd @sunway513

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@HAIAI

lcskrishna and others added 4 commits May 12, 2026 03:30
Resolved two conflicts in vllm/model_executor/layers/deepseek_v4_attention.py:

  * Decode path: dropped the
    ``VLLM_ROCM_USE_V4_TRITON_FALLBACK``-gated ``rocm_forward_decode_fallback``
    branch — upstream unified the call to ``flash_mla_with_kvcache`` for
    both CUDA and ROCm. The ROCm path is already routed to our
    ``flash_mla_with_kvcache_rocm`` Triton kernel via
    ``vllm.v1.attention.ops.flashmla`` (which already accepts the new
    ``is_fp8_kvcache``/``extra_k_cache``/``extra_indices_in_kvcache``
    kwargs).

  * Prefill path: dropped the env-gated branch around
    ``flash_mla_sparse_fwd`` and adopted upstream's signature (no longer
    returns a 3-tuple). Our ``flash_mla_sparse_fwd_rocm`` writes via
    ``out=`` so the return value is harmless to ignore.

Post-merge cleanup:

  * vllm/platforms/rocm.py: removed our duplicate "deepseek_v4_fp8"
    entry — upstream now adds it as the first member of
    ``supported_quantization``.

  * vllm/envs.py: trimmed the ``VLLM_ROCM_USE_V4_TRITON_FALLBACK``
    docstring from four call sites down to two (SWA K-cache writer and
    sparse indexer). The MLA decode / sparse-prefill paths are now
    permanently routed through the ROCm Triton fallbacks via flashmla.py
    on ROCm — no env-var toggle needed there any more.

Kept (still required after the merge):

  * vllm/model_executor/layers/sparse_attn_indexer.py — dispatch to
    ``rocm_sparse_attn_indexer_no_insert`` when
    skip_k_cache_insert + AITER disabled + env-var on.
  * vllm/v1/attention/ops/rocm_sparse_attn_indexer.py (recovered
    pre-rebase orchestration).
  * vllm/v1/attention/ops/rocm_flash_mla_sparse.py +
    flashmla.py ROCm dispatch.
  * vllm/model_executor/models/deepseek_v4.py:
    ``_resolve_deepseek_v4_expert_dtype`` — still required because
    upstream's new cached property only honours an explicit
    ``hf_config.expert_dtype`` and otherwise defaults to ``"fp4"``,
    misrouting FP8 checkpoints that ship without the field.
  * The Python SWA K-cache writer reference + env-gate around the
    HIPified ``fused_deepseek_v4_qnorm_rope_kv_rope_quant_insert``
    C++ kernel (still buggy on MI300X / FNUZ).

Backup tag: pre-upstream-merge-0512.

Co-authored-by: Cursor <cursoragent@cursor.com>
Upstream-added ``mhc_fused_post_pre`` calls three tilelang kernels
(``mhc_fused_tilelang``, ``mhc_post_tilelang``, ``mhc_pre_big_fuse_tilelang``)
that all use Program Dependent Launch (PDL — Hopper-only). On ROCm
tilelang's ``MarkCudaSyncCalls`` raises ``PDL is not supported`` at
JIT-compile time, taking down every TP worker during profile_run:

  [TileLang:...]: TileLang begins to compile kernel `mhc_post_tilelang`
  tvm.error.InternalError: Check failed: ... PDL is not supported

The non-fused ``mhc_pre`` and ``mhc_post`` already carry torch ROCm
fallbacks; this commit composes them to back the fused op on ROCm,
matching the contract (4-tuple of residual_cur / post_mix_cur /
comb_mix_cur / layer_input_cur with the exact same shapes and dtypes
as the tilelang path). The CUDA path is untouched.

This unblocks DSv4-Flash-Base-FP8 profile_run on MI300X after the
upstream merge that wired the fused op into the layer forward path.

Co-authored-by: Cursor <cursoragent@cursor.com>
@lcskrishna lcskrishna requested a review from zyongye as a code owner May 12, 2026 07:39
@tjtanaa
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tjtanaa commented May 12, 2026

We have landed triton sparse mla backend for dsv4 #41812 , and will land a aiter mhc PR #41946 that bugfix the dsv4 code path, remove the tilelang dependencies.

Can you help to check by then what we need to do to enable for DeepSeekV4-Flash-Base?

Moreover, we do not want to introduce more flags e.g. VLLM_ROCM_USE_V4_TRITON_FALLBACK

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lcskrishna commented May 12, 2026

Thanks @tjtanaa for providing an update on #41812 and #41946 - I believe I can drop the env variable once the PRs are merged. The following might be still needed though:

  • _resolve_deepseek-v4_expert_dtype in deepseek_v4.py which the lazy resolver defaults to fp4 and then the MoE routes through MXFP4 which throws an error.
  • fused_deepseek_v4_qnorm_rope_kv_rope_quant_insert -> The current codebase gives inconsistent results on various platforms (For ex: on MI300 - gives garbage output). So a fallback has been still added. I can go ahead and fix it inside C++ extension and create a seperate PR.
  • MoRI IO connector/ PD Disaggregation changes - I can split it into a newer PR.

Could you please share rough timeline of merging the #41946 which I can re-base and re-evaluate. Please let me know your thoughts.

cc: @wuhuikx @HAIAI

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lcskrishna commented May 18, 2026

FP8 Check point fixes - More robust way of using expert_dtype: #42970

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mergify Bot commented May 23, 2026

This pull request has merge conflicts that must be resolved before it can be
merged. Please rebase the PR, @lcskrishna.

https://docs.github.com/en/pull-requests/collaborating-with-pull-requests/working-with-forks/syncing-a-fork

@mergify mergify Bot added the needs-rebase label May 23, 2026
Fangzhou-Ai pushed a commit to Fangzhou-Ai/vllm that referenced this pull request May 26, 2026
Enable the DeepSeek V4 model setup to create the same three attention auxiliary streams on ROCm that CUDA already uses. This activates the existing decode overlap choreography for CSA: c4a layers can overlap the indexer pipeline, main KV compression, and SWA insertion, while c128a layers can overlap main KV compression with SWA insertion. XPU keeps the existing serial fallback, and CUDA behavior remains unchanged.

Duplicate-work check: issue vllm-project#41820 remains open; unauthenticated GitHub API searches found no open PR with "41820 in:body" and the closest open PRs from area keyword searches were vllm-project#41136 and vllm-project#41834, which cover ROCm enablement/fallbacks and NVIDIA SM12x support rather than this ROCm aux-stream gate.

Tests: .venv/bin/python -m pytest tests/models/test_deepseek_v4_rocm_multistream.py -q (3 passed, 16 warnings); pre-commit run ruff-check --files vllm/models/deepseek_v4/nvidia/model.py tests/models/test_deepseek_v4_rocm_multistream.py (passed); pre-commit run ruff-format --files vllm/models/deepseek_v4/nvidia/model.py tests/models/test_deepseek_v4_rocm_multistream.py (passed).

AI assistance was used for implementation and validation.
Fangzhou-Ai pushed a commit to Fangzhou-Ai/vllm that referenced this pull request May 26, 2026
Enable the DeepSeek V4 model setup to create the same three attention auxiliary streams on ROCm that CUDA already uses. This activates the existing decode overlap choreography for CSA: c4a layers can overlap the indexer pipeline, main KV compression, and SWA insertion, while c128a layers can overlap main KV compression with SWA insertion. XPU keeps the existing serial fallback, and CUDA behavior remains unchanged.

Duplicate-work check: issue vllm-project#41820 remains open; unauthenticated GitHub API searches found no open PR with "41820 in:body" and the closest open PRs from area keyword searches were vllm-project#41136 and vllm-project#41834, which cover ROCm enablement/fallbacks and NVIDIA SM12x support rather than this ROCm aux-stream gate.

Tests: .venv/bin/python -m pytest tests/models/test_deepseek_v4_rocm_multistream.py -q (3 passed, 16 warnings); pre-commit run ruff-check --files vllm/models/deepseek_v4/nvidia/model.py tests/models/test_deepseek_v4_rocm_multistream.py (passed); pre-commit run ruff-format --files vllm/models/deepseek_v4/nvidia/model.py tests/models/test_deepseek_v4_rocm_multistream.py (passed).

AI assistance was used for implementation and validation.

Signed-off-by: vLLM Contributor <contributor@vllm.ai>
Fangzhou-Ai pushed a commit to Fangzhou-Ai/vllm that referenced this pull request May 27, 2026
Enable the DeepSeek V4 model setup to create the same three attention auxiliary streams on ROCm that CUDA already uses. This activates the existing decode overlap choreography for CSA: c4a layers can overlap the indexer pipeline, main KV compression, and SWA insertion, while c128a layers can overlap main KV compression with SWA insertion. XPU keeps the existing serial fallback, and CUDA behavior remains unchanged.

Duplicate-work check: issue vllm-project#41820 remains open; unauthenticated GitHub API searches found no open PR with "41820 in:body" and the closest open PRs from area keyword searches were vllm-project#41136 and vllm-project#41834, which cover ROCm enablement/fallbacks and NVIDIA SM12x support rather than this ROCm aux-stream gate.

Tests: .venv/bin/python -m pytest tests/models/test_deepseek_v4_rocm_multistream.py -q (3 passed, 16 warnings); pre-commit run ruff-check --files vllm/models/deepseek_v4/nvidia/model.py tests/models/test_deepseek_v4_rocm_multistream.py (passed); pre-commit run ruff-format --files vllm/models/deepseek_v4/nvidia/model.py tests/models/test_deepseek_v4_rocm_multistream.py (passed).

AI assistance was used for implementation and validation.

Signed-off-by: vLLM Contributor <contributor@vllm.ai>
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