[Bugfix] Fix GLM-4 MoE router logits dtype for data parallel chunking#31055
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| # router_logits: (num_tokens, n_experts) | ||
| router_logits = self.gate(hidden_states.to(dtype=torch.float32)) | ||
| router_logits = self.gate(hidden_states.to(dtype=torch.float32)).to( | ||
| dtype=hidden_states.dtype | ||
| ) |
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The router output is now cast to hidden_states.dtype, so even in the default (non–DP-chunking) path GLM-4 MoE now runs softmax/top-k on bf16/fp16 instead of the float32 logits it previously produced by explicitly casting the input and keeping the gate weights in float32. This precision drop alters expert selection whenever chunking is not enabled, affecting inference quality across normal deployments; the chunking buffer mismatch could be resolved without changing the non-chunked routing dtype.
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Code Review
This pull request addresses a critical dtype mismatch issue that occurs when running GLM-4 MoE models with data parallel chunking, which previously led to an AssertionError. Your fix correctly resolves this by casting the router_logits to the expected data type. However, the current implementation applies this cast unconditionally, which could lead to a loss of precision and potentially affect model accuracy even when data parallel chunking is not in use. I've suggested a small refinement to make this cast conditional, applying it only when use_dp_chunking is active. This change will preserve the model's full precision for all other scenarios.
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Thanks for the work!
Is there any other way to fix this? I am worried changing dtype during forward, which may reduce performance
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Thanks for the feedback! I totally agree, I'm not comfortable with that change either. Here's how I see it, the issue is the assert that checks the buffer's dtype against the logits' dtypes right. So there are three solutions imho:
Let me know what you think is the best and I'll implement it right away 😄 I didn't go thoroughly through each MoE model's implementations especially since most of them don't suffer from this issue due to |
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GLM-4 MoE uses float32 for router logits but DP chunking buffers were allocated using in_dtype (bfloat16), causing dtype mismatch with pplx backend. This adds a configurable router_logits_dtype parameter to FusedMoE that defaults to in_dtype for backward compatibility, allowing models to specify float32 when needed. Signed-off-by: ReinforcedKnowledge <reinforced.knowledge@gmail.com>
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Hey! I've updated the PR to use a configurable |
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Hey! No worries at all! I've ran some E2E accuracy and performance testing, please let me know if they're not enough, or if you want me to optimize them for throughput or something else. I just used some values I knew would work out of the box but not necessarily optimal. The hardware is 8× NVIDIA H100 80GB GPUs. E2E accuracy test with TP=8 lm_eval --model vllm \
--model_args "pretrained=zai-org/GLM-4.6-FP8,tensor_parallel_size=8,enable_expert_parallel=true,add_bos_token=true,max_model_len=8192,gpu_memory_utilization=0.80,max_num_seqs=100" \
--tasks gsm8k \
--num_fewshot 5 \
--limit 1000 \
--batch_size autoResults:
Performance test with TP=8 vllm bench throughput \
--model zai-org/GLM-4.6-FP8 \
--tensor-parallel-size 8 \
--enable-expert-parallel \
--max-model-len 8192 \
--gpu-memory-utilization 0.80 \
--max-num-seqs 100 \
--input-len 2048 \
--output-len 512 \
--num-prompts 1000 \
--dataset-name randomResults:
The tests above do not go through the buggy path. The test below does: E2E accuracy test with TP=2 + DP=4 (validates DP chunking fix) VLLM_USE_FLASHINFER_MOE_FP8=1 lm_eval --model vllm \
--model_args "pretrained=zai-org/GLM-4.6-FP8,tensor_parallel_size=2,data_parallel_size=4,enable_expert_parallel=true,add_bos_token=true,max_model_len=8192,gpu_memory_utilization=0.80,max_num_seqs=20" \
--tasks gsm8k \
--num_fewshot 5 \
--limit 1000 \
--batch_size autoResults:
I didn't run the Also, I have noticed there are some failing CI checks, but I don't believe they're related to my changes. Happy to investigate further if needed. |
…vllm-project#31055) Signed-off-by: ReinforcedKnowledge <reinforced.knowledge@gmail.com>
…vllm-project#31055) Signed-off-by: ReinforcedKnowledge <reinforced.knowledge@gmail.com>
…vllm-project#31055) Signed-off-by: ReinforcedKnowledge <reinforced.knowledge@gmail.com> Signed-off-by: dsuhinin <suhinin.dmitriy@gmail.com>
…vllm-project#31055) Signed-off-by: ReinforcedKnowledge <reinforced.knowledge@gmail.com>
3 participants
Purpose
Fixes dtype mismatch in GLM4-MoE when using data parallel chunking with
--all2all-backend pplx.Root cause: GLM4-MoE uses float32 gates, but data parallel chunking pre-allocates buffers with the model's dtype (bfloat16). When
--all2all-backend pplxis used, chunking is enabled and the dtype assertion fails.The assertion that fails is this one: assert self.batched_router_logits.dtype == full_router_logits.dtype from
vllm/model_executor/layers/fused_moe/layer.py, permalink.The buffer is created with model's dtype in
ensure_dp_chunkingwithself.batched_router_logits = torch.zeros(logits_shape, dtype=moe.in_dtype, device=torch.cuda.current_device()), permalink.And the
moe.in_dtypecomes fromvllm_config.model_config.dtypeso in general it's a bfloat16.But GLM4's gates explicitly use float32, there is an explanation in the code that explains why they can't use
ReplicatedLinearas do some other MoEs and I think that's why this issue wasn't caught before or maybe wasn't caught by CI or something?The router logits are thus flaot32 as well
router_logits = self.gate(hidden_states.to(dtype=torch.float32))in the forward.So this causes a mismatch between the buffer's type and the actual logits.
The actual cause of this issue is not the simple mismatch, but the mismatch only happens when doing chunking. I thought it was the default but surprisingly it is not. When I disabled the pplx backend, I didn't get the error anymore. I think it's due to the conditions that check when to use dp chunking or not in
use_dp_chunking.So without the pplx backend, and without deepep kernels, the only way to trigger this is to use FP4. Which is surprising, and cool to learn haha
Conditions are:
I don't know if my fix is the best one.
I'm casting the router logits to bf16 (well, hidden states' dtype to be precise, which should be robust), so there's some loss of precision there.Note: Gemini's agent suggested we can useself.experts.use_dp_chunking, didn't think about that initially was too focused on reproducibility of my bug, but since accepting its suggestion didn't follow the commit message format I see in the git log and since my commit wasn't verified, I had to amend and squash.Test Plan
The following fails:
docker run --rm \ --gpus '"device=0,1,2,3,4,5,6,7"' \ --shm-size 10g \ -p 8011:8011 \ -v /mnt/nfs/username/hf_home:/root/.cache/huggingface/:rw \ -e VLLM_RPC_TIMEOUT=1800 \ vllm/vllm-openai:v0.13.0 \ --model zai-org/GLM-4.6-FP8 \ --served-model-name zai-org/GLM-4.6-FP8 \ --tensor-parallel-size 1 \ --data-parallel-size 8 \ --enable-expert-parallel \ --max-model-len 1024 \ --max-num-seqs 4 \ --max-num-batched-tokens 1024 \ --kv-cache-dtype fp8 \ --gpu-memory-utilization 0.85 \ --all2all-backend pplx \ --port 8000If we remove
--all2all-backend pplxit works. But my patch allows it to work with--all2all-backend pplxas well, to quick test it:docker run --rm \ --gpus '"device=0,1,2,3,4,5,6,7"' \ -p 8011:8011 \ -v /mnt/nfs/username/hf_home:/root/.cache/huggingface/:rw \ -v /path/to/patched/glm4_moe.py:/usr/local/lib/python3.12/dist-packages/vllm/model_executor/models/glm4_moe.py:ro \ -e VLLM_RPC_TIMEOUT=1800 \ vllm/vllm-openai:v0.13.0 \ --model zai-org/GLM-4.6-FP8 \ --served-model-name zai-org/GLM-4.6-FP8 \ --tensor-parallel-size 1 \ --data-parallel-size 8 \ --enable-expert-parallel \ --max-model-len 1024 \ --max-num-seqs 4 \ --max-num-batched-tokens 1024 \ --kv-cache-dtype fp8 \ --gpu-memory-utilization 0.85 \ --all2all-backend pplx \ --port 8000/path/to/patched/glm4_moe.py:is just the path to the file from my fork.Test Result
Before (without fix):
(EngineCore_DP1 pid=270) ERROR 12-19 17:14:18 [core.py:866] vllm/model_executor/layers/fused_moe/layer.py, line 1786, in forward_impl_chunked (EngineCore_DP1 pid=270) ERROR 12-19 17:14:18 [core.py:866] assert self.batched_router_logits.dtype == full_router_logits.dtype (EngineCore_DP1 pid=270) ERROR 12-19 17:14:18 [core.py:866] ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ (EngineCore_DP1 pid=270) ERROR 12-19 17:14:18 [core.py:866] AssertionErrorWorkaround (removing
--all2all-backend pplx): Works, but can't use PPLX optimizations.After (with fix): Server starts successfully with
--all2all-backend pplx.Related issue: #31056
Environment info
============================== System Info ============================== OS : Ubuntu 22.04.5 LTS (x86_64) GCC version : (Ubuntu 11.4.0-1ubuntu1~22.04) 11.4.0 Clang version : Could not collect CMake version : Could not collect Libc version : glibc-2.35 ============================== PyTorch Info ============================== PyTorch version : 2.9.1+cu128 Is debug build : False CUDA used to build PyTorch : 12.8 ROCM used to build PyTorch : N/A ============================== Python Environment ============================== Python version : 3.12.12 (main, Oct 28 2025, 12:10:49) [Clang 20.1.4 ] (64-bit runtime) Python platform : Linux-6.2.0-1015-nvidia-x86_64-with-glibc2.35 ============================== CUDA / GPU Info ============================== Is CUDA available : True CUDA runtime version : Could not collect CUDA_MODULE_LOADING set to : GPU models and configuration : GPU 0: NVIDIA H100 80GB HBM3 GPU 1: NVIDIA H100 80GB HBM3 GPU 2: NVIDIA H100 80GB HBM3 GPU 3: NVIDIA H100 80GB HBM3 GPU 4: NVIDIA H100 80GB HBM3 GPU 5: NVIDIA H100 80GB HBM3 GPU 6: NVIDIA H100 80GB HBM3 GPU 7: NVIDIA H100 80GB HBM3 Nvidia driver version : 550.90.07 cuDNN version : Could not collect HIP runtime version : N/A MIOpen runtime version : N/A Is XNNPACK available : True ============================== CPU Info ============================== Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Address sizes: 52 bits physical, 57 bits virtual Byte Order: Little Endian CPU(s): 144 On-line CPU(s) list: 0-143 Vendor ID: GenuineIntel Model name: Intel(R) Xeon(R) Platinum 8452Y CPU family: 6 Model: 143 Thread(s) per core: 2 Core(s) per socket: 36 Socket(s): 2 Stepping: 8 CPU max MHz: 3200,0000 CPU min MHz: 800,0000 BogoMIPS: 4000.00 Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cat_l2 cdp_l3 invpcid_single intel_ppin cdp_l2 ssbd mba ibrs ibpb stibp ibrs_enhanced tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a avx512f avx512dq rdseed adx smap avx512ifma clflushopt clwb intel_pt avx512cd sha_ni avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local split_lock_detect avx_vnni avx512_bf16 wbnoinvd dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req hfi avx512vbmi umip pku ospke waitpkg avx512_vbmi2 gfni vaes vpclmulqdq avx512_vnni avx512_bitalg tme avx512_vpopcntdq la57 rdpid bus_lock_detect cldemote movdiri movdir64b enqcmd fsrm md_clear serialize tsxldtrk pconfig arch_lbr ibt amx_bf16 avx512_fp16 amx_tile amx_int8 flush_l1d arch_capabilities Virtualization: VT-x L1d cache: 3,4 MiB (72 instances) L1i cache: 2,3 MiB (72 instances) L2 cache: 144 MiB (72 instances) L3 cache: 135 MiB (2 instances) NUMA node(s): 2 NUMA node0 CPU(s): 0-35,72-107 NUMA node1 CPU(s): 36-71,108-143 Vulnerability Gather data sampling: Not affected Vulnerability Itlb multihit: Not affected Vulnerability L1tf: Not affected Vulnerability Mds: Not affected Vulnerability Meltdown: Not affected Vulnerability Mmio stale data: Not affected Vulnerability Retbleed: Not affected Vulnerability Spec rstack overflow: Not affected Vulnerability Spec store bypass: Mitigation; Speculative Store Bypass disabled via prctl Vulnerability Spectre v1: Mitigation; usercopy/swapgs barriers and __user pointer sanitization Vulnerability Spectre v2: Mitigation; Enhanced IBRS, IBPB conditional, RSB filling, PBRSB-eIBRS SW sequence Vulnerability Srbds: Not affected Vulnerability Tsx async abort: Not affected ============================== Versions of relevant libraries ============================== [pip3] numpy==2.3.5 [pip3] nvidia-cublas-cu12==12.8.4.1 [pip3] nvidia-cuda-cupti-cu12==12.8.90 [pip3] nvidia-cuda-nvrtc-cu12==12.8.93 [pip3] nvidia-cuda-runtime-cu12==12.8.90 [pip3] nvidia-cudnn-cu12==9.10.2.21 [pip3] nvidia-cufft-cu12==11.3.3.83 [pip3] nvidia-cufile-cu12==1.13.1.3 [pip3] nvidia-curand-cu12==10.3.9.90 [pip3] nvidia-cusolver-cu12==11.7.3.90 [pip3] nvidia-cusparse-cu12==12.5.8.93 [pip3] nvidia-cusparselt-cu12==0.7.1 [pip3] nvidia-nccl-cu12==2.27.5 [pip3] nvidia-nvjitlink-cu12==12.8.93 [pip3] nvidia-nvshmem-cu12==3.3.20 [pip3] nvidia-nvtx-cu12==12.8.90 [pip3] torch==2.9.1 [pip3] triton==3.5.1 [conda] Could not collect ============================== vLLM Info ============================== ROCM Version : Could not collect vLLM Version : 0.14.0rc1.dev7+g9187de9fa.d20251220 (git sha: 9187de9fa, date: 20251220) vLLM Build Flags: CUDA Archs: Not Set; ROCm: Disabled GPU Topology: GPU0 GPU1 GPU2 GPU3 GPU4 GPU5 GPU6 GPU7 NIC0 NIC1 NIC2 NIC3 NIC4 NIC5 NIC6 NIC7 NIC8 NIC9 NIC10 CPU Affinity NUMA Affinity GPU NUMA ID GPU0 X NV18 NV18 NV18 NV18 NV18 NV18 NV18 PIX PXB NODE NODE NODE NODE SYS SYS SYS SYS NODE 0-35,72-107 0 N/A GPU1 NV18 X NV18 NV18 NV18 NV18 NV18 NV18 PXB PIX NODE NODE NODE NODE SYS SYS SYS SYS NODE 0-35,72-107 0 N/A GPU2 NV18 NV18 X NV18 NV18 NV18 NV18 NV18 NODE NODE PIX PXB NODE NODE SYS SYS SYS SYS NODE 0-35,72-107 0 N/A GPU3 NV18 NV18 NV18 X NV18 NV18 NV18 NV18 NODE NODE PXB PIX NODE NODE SYS SYS SYS SYS NODE 0-35,72-107 0 N/A GPU4 NV18 NV18 NV18 NV18 X NV18 NV18 NV18 SYS SYS SYS SYS SYS SYS PIX PXB NODE NODE SYS 36-71,108-143 1 N/A GPU5 NV18 NV18 NV18 NV18 NV18 X NV18 NV18 SYS SYS SYS SYS SYS SYS PXB PIX NODE NODE SYS 36-71,108-143 1 N/A GPU6 NV18 NV18 NV18 NV18 NV18 NV18 X NV18 SYS SYS SYS SYS SYS SYS NODE NODE PIX PXB SYS 36-71,108-143 1 N/A GPU7 NV18 NV18 NV18 NV18 NV18 NV18 NV18 X SYS SYS SYS SYS SYS SYS NODE NODE PXB PIX SYS 36-71,108-143 1 N/A NIC0 PIX PXB NODE NODE SYS SYS SYS SYS X PXB NODE NODE NODE NODE SYS SYS SYS SYS NODE NIC1 PXB PIX NODE NODE SYS SYS SYS SYS PXB X NODE NODE NODE NODE SYS SYS SYS SYS NODE NIC2 NODE NODE PIX PXB SYS SYS SYS SYS NODE NODE X PXB NODE NODE SYS SYS SYS SYS NODE NIC3 NODE NODE PXB PIX SYS SYS SYS SYS NODE NODE PXB X NODE NODE SYS SYS SYS SYS NODE NIC4 NODE NODE NODE NODE SYS SYS SYS SYS NODE NODE NODE NODE X PIX SYS SYS SYS SYS NODE NIC5 NODE NODE NODE NODE SYS SYS SYS SYS NODE NODE NODE NODE PIX X SYS SYS SYS SYS NODE NIC6 SYS SYS SYS SYS PIX PXB NODE NODE SYS SYS SYS SYS SYS SYS X PXB NODE NODE SYS NIC7 SYS SYS SYS SYS PXB PIX NODE NODE SYS SYS SYS SYS SYS SYS PXB X NODE NODE SYS NIC8 SYS SYS SYS SYS NODE NODE PIX PXB SYS SYS SYS SYS SYS SYS NODE NODE X PXB SYS NIC9 SYS SYS SYS SYS NODE NODE PXB PIX SYS SYS SYS SYS SYS SYS NODE NODE PXB X SYS NIC10 NODE NODE NODE NODE SYS SYS SYS SYS NODE NODE NODE NODE NODE NODE SYS SYS SYS SYS X Legend: X = Self SYS = Connection traversing PCIe as well as the SMP interconnect between NUMA nodes (e.g., QPI/UPI) NODE = Connection traversing PCIe as well as the interconnect between PCIe Host Bridges within a NUMA node PHB = Connection traversing PCIe as well as a PCIe Host Bridge (typically the CPU) PXB = Connection traversing multiple PCIe bridges (without traversing the PCIe Host Bridge) PIX = Connection traversing at most a single PCIe bridge NV# = Connection traversing a bonded set of # NVLinks NIC Legend: NIC0: mlx5_0 NIC1: mlx5_1 NIC2: mlx5_2 NIC3: mlx5_3 NIC4: mlx5_4 NIC5: mlx5_5 NIC6: mlx5_8 NIC7: mlx5_9 NIC8: mlx5_10 NIC9: mlx5_11 NIC10: mlx5_bond_0 ============================== Environment Variables ============================== PYTORCH_NVML_BASED_CUDA_CHECK=1 TORCHINDUCTOR_COMPILE_THREADS=1