[310P]fused recurrent gated delta rule pytorch core and ut - #7398
wangxiyuan merged 3 commits into
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Summary of ChangesHello, I'm Gemini Code Assist1! I'm currently reviewing this pull request and will post my feedback shortly. In the meantime, here's a summary to help you and other reviewers quickly get up to speed! This pull request introduces a crucial PyTorch fallback implementation for the Highlights
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Code Review
This pull request introduces a PyTorch reference implementation for the fused_recurrent_gated_delta_rule and a corresponding unit test. The implementation is for Ascend 310P devices. My review has identified a critical bug in the state indexing logic that could lead to incorrect behavior when using ssm_state_indices. I have provided a detailed comment with a suggested fix. Additionally, I've recommended enhancing the unit tests to cover this complex part of the logic to prevent future regressions.
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This pull request has conflicts, please resolve those before we can evaluate the pull request. |
…test Signed-off-by: Tflowers-0129 <2906339855@qq.com>
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…ect#7398) ### What this PR does / why we need it? RFC vllm-project#7394 Add a PyTorch implementation of the fused recurrent gated delta ruler on 310P. ### Does this PR introduce _any_ user-facing change? NO ### How was this patch tested? UT - vLLM version: v0.17.0 - vLLM main: vllm-project/vllm@4497431 --------- Signed-off-by: Tflowers-0129 <2906339855@qq.com> Co-authored-by: wangxiyuan <wangxiyuan1007@gmail.com>
…to qwen3next_graph * 'main' of https://github.com/vllm-project/vllm-ascend: (94 commits) [bugfix] Fixed the error issue when overlaying MTP and full decode on DSV3.1 C8. (vllm-project#7571) [eagle3][pcp] fix acceptance rate for eagle3 and pcp enabled (vllm-project#7549) [bugfix][CI] fix '_OpNamespace' 'vllm' object has no attribute 'qkv_rmsnorm_rope' (vllm-project#7620) [Nightly] Nightly pre-build image (vllm-project#7388) [Bugfix]Fix deepseek 3.2 C8 precision by rotary tensor (vllm-project#7537) adapt to main2main for model runner v2 (vllm-project#7578) [Patch] Fix balance scheduling (vllm-project#7611) [310P]fused recurrent gated delta rule pytorch core and ut (vllm-project#7398) [CI] refine issue triage rules, wan regex and update stale setting (vllm-project#7531) [Lint]Add lint hooks for clang-format, shellcheck, forbidden imports, and boolean context manager checks (vllm-project#7511) [doc] add enable_sparse_c8 option in configuration options (vllm-project#7600) lower log level in PD Disaggregation (vllm-project#7589) [model_runner_v2]:optimize the performance of the _compute_slot_mappings_kernel (vllm-project#7575) [Feat][SP] Suport SP for VL MoE models (vllm-project#7044) Fix Qwen3Next CI Config (vllm-project#7561) [Feat] Add npugraph_ex enablement logging (vllm-project#7574) [UT] Align input arguments with Ascend(Yarn)RotaryEmbedding with vLLM and add ut (vllm-project#7358) [P/D] Check wildcard address for layerwise connector (vllm-project#7389) [P/D] [Bugfix] fix mooncake layerconnector dead when update_decoder_info fail (vllm-project#7514) [BugFix][P/D] fix padding error on FullGraph mode && fix layerwise connector mamba accuracy (vllm-project#7506) ...
…ect#7398) ### What this PR does / why we need it? RFC vllm-project#7394 Add a PyTorch implementation of the fused recurrent gated delta ruler on 310P. ### Does this PR introduce _any_ user-facing change? NO ### How was this patch tested? UT - vLLM version: v0.17.0 - vLLM main: vllm-project/vllm@4497431 --------- Signed-off-by: Tflowers-0129 <2906339855@qq.com> Co-authored-by: wangxiyuan <wangxiyuan1007@gmail.com>
…ect#7398) ### What this PR does / why we need it? RFC vllm-project#7394 Add a PyTorch implementation of the fused recurrent gated delta ruler on 310P. ### Does this PR introduce _any_ user-facing change? NO ### How was this patch tested? UT - vLLM version: v0.17.0 - vLLM main: vllm-project/vllm@4497431 --------- Signed-off-by: Tflowers-0129 <2906339855@qq.com> Co-authored-by: wangxiyuan <wangxiyuan1007@gmail.com>
…ect#7398) ### What this PR does / why we need it? RFC vllm-project#7394 Add a PyTorch implementation of the fused recurrent gated delta ruler on 310P. ### Does this PR introduce _any_ user-facing change? NO ### How was this patch tested? UT - vLLM version: v0.17.0 - vLLM main: vllm-project/vllm@4497431 --------- Signed-off-by: Tflowers-0129 <2906339855@qq.com> Co-authored-by: wangxiyuan <wangxiyuan1007@gmail.com> Signed-off-by: zouyida2052 <zouyida2002@gmail.com>
…ect#7398) ### What this PR does / why we need it? RFC vllm-project#7394 Add a PyTorch implementation of the fused recurrent gated delta ruler on 310P. ### Does this PR introduce _any_ user-facing change? NO ### How was this patch tested? UT - vLLM version: v0.17.0 - vLLM main: vllm-project/vllm@4497431 --------- Signed-off-by: Tflowers-0129 <2906339855@qq.com> Co-authored-by: wangxiyuan <wangxiyuan1007@gmail.com>
…ect#7398) ### What this PR does / why we need it? RFC vllm-project#7394 Add a PyTorch implementation of the fused recurrent gated delta ruler on 310P. ### Does this PR introduce _any_ user-facing change? NO ### How was this patch tested? UT - vLLM version: v0.17.0 - vLLM main: vllm-project/vllm@4497431 --------- Signed-off-by: Tflowers-0129 <2906339855@qq.com> Co-authored-by: wangxiyuan <wangxiyuan1007@gmail.com> Signed-off-by: nanxing <1014662416@qq.com>
SP-0a A0a.11 + A0a.12 deliverables. A0a.11 — fill jh-architecture.md «Version freeze» с реальными values из image inspection: - OS: Ubuntu 22.04.5 LTS - CANN: 8.5.1 - torch: 2.9.0+cpu, torch_npu: 2.9.0 - transformers: 5.5.3, vllm: 0.19.1+empty, vllm_ascend: 0.19.1rc1 - Host driver: 26.0.rc1 (ascendhal 7.35.23) - Our Harbor image: cr.jethome.work/jethome-iot/vllm-ascend:jh-stable (sha256:0c7122525de75...) A0a.12 — docs/jh-upstream-status.md initial с current status 9 critical PR/issues (vllm-project#7394, vllm-project#7306, vllm-project#7398, vllm-project#7798, vllm-project#7109, vllm-project#3017, vllm-project#1565, vllm-project#1700, vllm-project#5318). Также fix branch naming convention в PR strategy section — `jh-feature/<sub>` instead of `jh/qwen36-310p/<sub>` (git ref doesn't allow file/dir coexistence).
SP-0a A0a.11 + A0a.12 deliverables. A0a.11 — fill jh-architecture.md «Version freeze» с реальными values из image inspection: - OS: Ubuntu 22.04.5 LTS - CANN: 8.5.1 - torch: 2.9.0+cpu, torch_npu: 2.9.0 - transformers: 5.5.3, vllm: 0.19.1+empty, vllm_ascend: 0.19.1rc1 - Host driver: 26.0.rc1 (ascendhal 7.35.23) - Our Harbor image: cr.jethome.work/jethome-iot/vllm-ascend:jh-stable (sha256:0c7122525de75...) A0a.12 — docs/jh-upstream-status.md initial с current status 9 critical PR/issues (vllm-project#7394, vllm-project#7306, vllm-project#7398, vllm-project#7798, vllm-project#7109, vllm-project#3017, vllm-project#1565, vllm-project#1700, vllm-project#5318). Также fix branch naming convention в PR strategy section — `jh-feature/<sub>` instead of `jh/qwen36-310p/<sub>` (git ref doesn't allow file/dir coexistence).
SP-1 A1a.0 investigation revealed что upstream `vllm-ascend` уже merged большинство fixes планировавшихся как наша работа (PyTorch fallback decode/chunk, patch_qwen3_5). PR vllm-project#9514 (merged 2026-05-30) addresses vllm-project#7306 MambaSpec dtype. Decision: rebase jh/main onto upstream/main HEAD (a8658e9) + reduce SP-1 scope to verify-only (skip ABI/stub kernel — defer to SP-3 on real signature basis). Backup tag: pre-rebase-2026-05-30 (732f7f8) для recovery. Refs: - huawei-ascend/docs/investigations/2026-05-30-sp1-scope-shift.md - PRs vllm-project#7109, vllm-project#7398, vllm-project#7306, vllm-project#9514
SP-0a A0a.11 + A0a.12 deliverables. A0a.11 — fill jh-architecture.md «Version freeze» с реальными values из image inspection: - OS: Ubuntu 22.04.5 LTS - CANN: 8.5.1 - torch: 2.9.0+cpu, torch_npu: 2.9.0 - transformers: 5.5.3, vllm: 0.19.1+empty, vllm_ascend: 0.19.1rc1 - Host driver: 26.0.rc1 (ascendhal 7.35.23) - Our Harbor image: cr.jethome.work/jethome-iot/vllm-ascend:jh-stable (sha256:0c7122525de75...) A0a.12 — docs/jh-upstream-status.md initial с current status 9 critical PR/issues (vllm-project#7394, vllm-project#7306, vllm-project#7398, vllm-project#7798, vllm-project#7109, vllm-project#3017, vllm-project#1565, vllm-project#1700, vllm-project#5318). Также fix branch naming convention в PR strategy section — `jh-feature/<sub>` instead of `jh/qwen36-310p/<sub>` (git ref doesn't allow file/dir coexistence).
SP-1 A1a.0 investigation revealed что upstream `vllm-ascend` уже merged большинство fixes планировавшихся как наша работа (PyTorch fallback decode/chunk, patch_qwen3_5). PR vllm-project#9514 (merged 2026-05-30) addresses vllm-project#7306 MambaSpec dtype. Decision: rebase jh/main onto upstream/main HEAD (a8658e9) + reduce SP-1 scope to verify-only (skip ABI/stub kernel — defer to SP-3 on real signature basis). Backup tag: pre-rebase-2026-05-30 (732f7f8) для recovery. Refs: - huawei-ascend/docs/investigations/2026-05-30-sp1-scope-shift.md - PRs vllm-project#7109, vllm-project#7398, vllm-project#7306, vllm-project#9514
…ect#7398) ### What this PR does / why we need it? RFC vllm-project#7394 Add a PyTorch implementation of the fused recurrent gated delta ruler on 310P. ### Does this PR introduce _any_ user-facing change? NO ### How was this patch tested? UT - vLLM version: v0.17.0 - vLLM main: vllm-project/vllm@4497431 --------- Signed-off-by: Tflowers-0129 <2906339855@qq.com> Co-authored-by: wangxiyuan <wangxiyuan1007@gmail.com>
…ect#7398) ### What this PR does / why we need it? RFC vllm-project#7394 Add a PyTorch implementation of the fused recurrent gated delta ruler on 310P. ### Does this PR introduce _any_ user-facing change? NO ### How was this patch tested? UT - vLLM version: v0.17.0 - vLLM main: vllm-project/vllm@4497431 --------- Signed-off-by: Tflowers-0129 <2906339855@qq.com> Co-authored-by: wangxiyuan <wangxiyuan1007@gmail.com>
What this PR does / why we need it?
RFC #7394
Add a PyTorch implementation of the fused recurrent gated delta ruler on 310P.
Does this PR introduce any user-facing change?
NO
How was this patch tested?
UT