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[Kernel]: Optimize DispatchFFNCombine performance#6468

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zzzzwwjj merged 3 commits intovllm-project:mainfrom
serlar:perf_opt
Feb 9, 2026
Merged

[Kernel]: Optimize DispatchFFNCombine performance#6468
zzzzwwjj merged 3 commits intovllm-project:mainfrom
serlar:perf_opt

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@serlar serlar commented Feb 1, 2026

What this PR does / why we need it?

This PR focuses on performance optimization for the DispatchFFNCombine operator. The key optimizations include:

  1. Improving communication efficiency by merging the transmission of tokens and scales;
  2. Decoupling multi-core dependencies and reducing waiting bubbles in the combine process through tile-granularity communication;
  3. Optimizing the full-card synchronization overhead before the umpermute operation.

These optimizations aim to reduce the overall execution latency of the DispatchFFNCombine operator and enhance the runtime performance of the model inference process on Ascend devices.

Does this PR introduce any user-facing change?

No. This PR only involves internal performance optimization of the DispatchFFNCombine operator and does not introduce any changes to user-facing APIs, interfaces, or behaviors.

How was this patch tested?

  1. Enable the DispatchFFNCombine operator by setting the environment variable:
export VLLM_ASCEND_ENABLE_FUSED_MC2=1
  1. Run the standard model inference test suite with the above environment variable enabled;
  2. Verify the correctness of model outputs (ensuring no functional regression) and measure the performance improvement of the DispatchFFNCombine operator (reduced latency and improved throughput).

@serlar serlar requested a review from zzzzwwjj as a code owner February 1, 2026 10:14
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github-actions Bot commented Feb 1, 2026

👋 Hi! Thank you for contributing to the vLLM Ascend project. The following points will speed up your PR merge:‌‌

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Summary of Changes

Hello @serlar, I'm Gemini Code Assist1! I'm currently reviewing this pull request and will post my feedback shortly. In the meantime, here's a summary to help you and other reviewers quickly get up to speed!

This pull request significantly enhances the performance of the DispatchFFNCombine operator, specifically targeting Ascend devices. The core improvements revolve around optimizing inter-core communication by transmitting tokens and their quantization scales together, and by implementing a more efficient, flag-based synchronization mechanism across processing units. These internal changes are designed to reduce execution latency and boost model inference throughput without impacting any user-facing APIs or behaviors.

Highlights

  • Merged Token and Scale Transmission: The pull request introduces a significant optimization by merging the transmission of tokens and their corresponding scales. This is achieved through the new CopyGMToGMPerToken function and modifications in the quantization headers (moe_v2_fullload_dynamic_quant.h, moe_v2_gather_dynamic_quant.h) which now allocate combined buffer space (cols_scale_) for both data and scale, improving communication efficiency.
  • Optimized Full-Card Synchronization: Synchronization overhead before the unpermute operation has been optimized. New functions like InitArithProgress, CrossRankSyncV2Set, and CrossRankSyncV2Wait in hccl_shmem.hpp implement a more efficient cross-rank synchronization mechanism using soft flags. The BlockMmad class now incorporates this new flag-based synchronization, reducing latency.
  • Refactored Kernel Logic: The DispatchFFNCombineKernel has been refactored to merge the Dispatch and Combine operations into a single DispatchAndCombine function. This streamlines the execution flow and simplifies the kernel's overall structure. Additionally, several kernel configurations have been consolidated, and local weight/scale arrays have been removed in favor of direct GetTensorAddr calls for better memory management.
  • Enhanced Workspace Management: Workspace allocation for the DispatchFFNCombine operator has been refined. The cocWorkspace calculation in dispatch_ffn_combine_tiling.cpp now includes additional space for synchronization-related data. The WorkspaceInfo struct in dispatch_ffn_combine_kernel.hpp has been updated to separate ptrC and ptrC2, and ptrPermutedToken and ptrA, along with new allocations for ptrSumBeforeRank and ptrSoftFlagBase.
  • New Epilogue Dispatch Policy: A new epilogue dispatch policy, EpilogueAtlasA2PerTokenDequantV2, has been introduced and implemented in block_epilogue_pertoken_v2.hpp. This new policy is designed to handle the dequantization and result writing in conjunction with the merged token and scale data, utilizing ping-pong buffers for efficient data processing.

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Code Review

This pull request introduces significant performance optimizations for the DispatchFFNCombine operator. The changes focus on improving communication efficiency by merging the transmission of tokens and scales, and on optimizing the synchronization overhead. The implementation involves substantial refactoring across multiple kernel files, including the introduction of new epilogue and synchronization logic.

The review has identified a critical compilation error due to a typo in an #include directive. Additionally, a couple of high-severity issues have been found, including another typo in an include guard and a potential reduction in functionality where a specific case is now handled by trap(), which could lead to runtime failures for certain inputs.

Comment thread csrc/dispatch_ffn_combine/op_kernel/dispatch_ffn_combine_kernel.hpp Outdated
Signed-off-by: xulei_ict <xulei292@huawei.com>
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github-actions Bot commented Feb 2, 2026

This pull request has conflicts, please resolve those before we can evaluate the pull request.

@serlar serlar changed the title perf: Optimize DispatchFFNCombine performance [Kernel]: Optimize DispatchFFNCombine performance Feb 2, 2026
@wangxiyuan wangxiyuan added ready read for review ready-for-test start test by label for PR labels Feb 2, 2026
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github-actions Bot commented Feb 3, 2026

This pull request has conflicts, please resolve those before we can evaluate the pull request.

@zzzzwwjj zzzzwwjj merged commit 8325528 into vllm-project:main Feb 9, 2026
17 checks passed
845473182 pushed a commit to 845473182/vllm-ascend that referenced this pull request Feb 11, 2026
…to qwen3next_rebase

* 'main' of https://github.com/vllm-project/vllm-ascend:
  [Feat] 310p support MoE W8A8 quantizaition (vllm-project#6641)
  [TEST]add a qwen3-30b acc case with mooncake mempool (vllm-project#6244)
  [MOE Refactor] Remove QuantType in prepare_finalize.py (vllm-project#6534)
  [EPLB] Avoiding eplb's dependency on a specified model (vllm-project#6528)
  [Doc][Misc] Restructure tutorial documentation (vllm-project#6501)
  implement batch invariant with ascendc (vllm-project#6590)
  [Refact]Refact MLA/SFA weight prefetch to consist with moe weight prefetch (vllm-project#6629)
  [Misc] upgrade to vllm main (vllm-project#6646)
  [main][Docs] Fix spelling errors across documentation (vllm-project#6649)
  [bugfix]Fix no attribute 'data' when MLAPO is enable  (vllm-project#6601)
  [DOC]Add Memcache Usage Guide (vllm-project#6476)
  [main][bugfix] Fix spec acceptance rate problem in vllm_0.15.0 (vllm-project#6606)
  [Test][LoRA] Add e2e test for base model inference (vllm-project#6624)
  [refactor]Optimized the kvcache usage of Deepseek v3.2 (vllm-project#6610)
  [Feat](sfa,dcp) support dcp for sfa (vllm-project#6563)
  [BugFix] Add support for rotary_dim parameter when using partial rope in rotary_embedding (vllm-project#6581)
  [fix bug] fix tensor mismatch bug in sigmoid operate test case (vllm-project#6619)
  [Kernel]: Optimize DispatchFFNCombine performance (vllm-project#6468)
  [MISC] Clean up useless env USE_OPTIMIZED_MODEL (vllm-project#6618)
chenchuw886 pushed a commit to chenchuw886/vllm-ascend that referenced this pull request Feb 12, 2026
### What this PR does / why we need it?

This PR focuses on performance optimization for the DispatchFFNCombine
operator. The key optimizations include:

1. Improving communication efficiency by merging the transmission of
tokens and scales;
2. Decoupling multi-core dependencies and reducing waiting bubbles in
the combine process through tile-granularity communication;
3. Optimizing the full-card synchronization overhead before the
umpermute operation.

These optimizations aim to reduce the overall execution latency of the
DispatchFFNCombine operator and enhance the runtime performance of the
model inference process on Ascend devices.

### Does this PR introduce _any_ user-facing change?

No. This PR only involves internal performance optimization of the
DispatchFFNCombine operator and does not introduce any changes to
user-facing APIs, interfaces, or behaviors.

### How was this patch tested?

1. Enable the DispatchFFNCombine operator by setting the environment
variable:
```
export VLLM_ASCEND_ENABLE_FUSED_MC2=1
```
2. Run the standard model inference test suite with the above
environment variable enabled;
4. Verify the correctness of model outputs (ensuring no functional
regression) and measure the performance improvement of the
DispatchFFNCombine operator (reduced latency and improved throughput).

- vLLM version: v0.14.1
- vLLM main:
vllm-project/vllm@dc917cc

Signed-off-by: xulei_ict <xulei292@huawei.com>
Co-authored-by: xulei_ict <xulei292@huawei.com>
Signed-off-by: momochenchuw <chenchuw@huawei.com>
@wangxiyuan wangxiyuan mentioned this pull request Feb 24, 2026
ZRJ026 pushed a commit to ZRJ026/vllm-ascend that referenced this pull request Feb 28, 2026
### What this PR does / why we need it?

This PR focuses on performance optimization for the DispatchFFNCombine
operator. The key optimizations include:

1. Improving communication efficiency by merging the transmission of
tokens and scales;
2. Decoupling multi-core dependencies and reducing waiting bubbles in
the combine process through tile-granularity communication;
3. Optimizing the full-card synchronization overhead before the
umpermute operation.

These optimizations aim to reduce the overall execution latency of the
DispatchFFNCombine operator and enhance the runtime performance of the
model inference process on Ascend devices.

### Does this PR introduce _any_ user-facing change?

No. This PR only involves internal performance optimization of the
DispatchFFNCombine operator and does not introduce any changes to
user-facing APIs, interfaces, or behaviors.

### How was this patch tested?

1. Enable the DispatchFFNCombine operator by setting the environment
variable:
```
export VLLM_ASCEND_ENABLE_FUSED_MC2=1
```
2. Run the standard model inference test suite with the above
environment variable enabled;
4. Verify the correctness of model outputs (ensuring no functional
regression) and measure the performance improvement of the
DispatchFFNCombine operator (reduced latency and improved throughput).

- vLLM version: v0.14.1
- vLLM main:
vllm-project/vllm@dc917cc

Signed-off-by: xulei_ict <xulei292@huawei.com>
Co-authored-by: xulei_ict <xulei292@huawei.com>
Signed-off-by: zrj026 <zhangrunjiang026@gmail.com>
maoxx241 pushed a commit to maoxx241/vllm-ascend that referenced this pull request Mar 2, 2026
### What this PR does / why we need it?

This PR focuses on performance optimization for the DispatchFFNCombine
operator. The key optimizations include:

1. Improving communication efficiency by merging the transmission of
tokens and scales;
2. Decoupling multi-core dependencies and reducing waiting bubbles in
the combine process through tile-granularity communication;
3. Optimizing the full-card synchronization overhead before the
umpermute operation.

These optimizations aim to reduce the overall execution latency of the
DispatchFFNCombine operator and enhance the runtime performance of the
model inference process on Ascend devices.

### Does this PR introduce _any_ user-facing change?

No. This PR only involves internal performance optimization of the
DispatchFFNCombine operator and does not introduce any changes to
user-facing APIs, interfaces, or behaviors.

### How was this patch tested?

1. Enable the DispatchFFNCombine operator by setting the environment
variable:
```
export VLLM_ASCEND_ENABLE_FUSED_MC2=1
```
2. Run the standard model inference test suite with the above
environment variable enabled;
4. Verify the correctness of model outputs (ensuring no functional
regression) and measure the performance improvement of the
DispatchFFNCombine operator (reduced latency and improved throughput).

- vLLM version: v0.14.1
- vLLM main:
vllm-project/vllm@dc917cc

Signed-off-by: xulei_ict <xulei292@huawei.com>
Co-authored-by: xulei_ict <xulei292@huawei.com>
ZRJ026 pushed a commit to ZRJ026/vllm-ascend that referenced this pull request Mar 4, 2026
### What this PR does / why we need it?

This PR focuses on performance optimization for the DispatchFFNCombine
operator. The key optimizations include:

1. Improving communication efficiency by merging the transmission of
tokens and scales;
2. Decoupling multi-core dependencies and reducing waiting bubbles in
the combine process through tile-granularity communication;
3. Optimizing the full-card synchronization overhead before the
umpermute operation.

These optimizations aim to reduce the overall execution latency of the
DispatchFFNCombine operator and enhance the runtime performance of the
model inference process on Ascend devices.

### Does this PR introduce _any_ user-facing change?

No. This PR only involves internal performance optimization of the
DispatchFFNCombine operator and does not introduce any changes to
user-facing APIs, interfaces, or behaviors.

### How was this patch tested?

1. Enable the DispatchFFNCombine operator by setting the environment
variable:
```
export VLLM_ASCEND_ENABLE_FUSED_MC2=1
```
2. Run the standard model inference test suite with the above
environment variable enabled;
4. Verify the correctness of model outputs (ensuring no functional
regression) and measure the performance improvement of the
DispatchFFNCombine operator (reduced latency and improved throughput).

- vLLM version: v0.14.1
- vLLM main:
vllm-project/vllm@dc917cc

Signed-off-by: xulei_ict <xulei292@huawei.com>
Co-authored-by: xulei_ict <xulei292@huawei.com>
Signed-off-by: zrj026 <zhangrunjiang026@gmail.com>
LCAIZJ pushed a commit to LCAIZJ/vllm-ascend that referenced this pull request Mar 7, 2026
### What this PR does / why we need it?

This PR focuses on performance optimization for the DispatchFFNCombine
operator. The key optimizations include:

1. Improving communication efficiency by merging the transmission of
tokens and scales;
2. Decoupling multi-core dependencies and reducing waiting bubbles in
the combine process through tile-granularity communication;
3. Optimizing the full-card synchronization overhead before the
umpermute operation.

These optimizations aim to reduce the overall execution latency of the
DispatchFFNCombine operator and enhance the runtime performance of the
model inference process on Ascend devices.

### Does this PR introduce _any_ user-facing change?

No. This PR only involves internal performance optimization of the
DispatchFFNCombine operator and does not introduce any changes to
user-facing APIs, interfaces, or behaviors.

### How was this patch tested?

1. Enable the DispatchFFNCombine operator by setting the environment
variable:
```
export VLLM_ASCEND_ENABLE_FUSED_MC2=1
```
2. Run the standard model inference test suite with the above
environment variable enabled;
4. Verify the correctness of model outputs (ensuring no functional
regression) and measure the performance improvement of the
DispatchFFNCombine operator (reduced latency and improved throughput).

- vLLM version: v0.14.1
- vLLM main:
vllm-project/vllm@dc917cc

Signed-off-by: xulei_ict <xulei292@huawei.com>
Co-authored-by: xulei_ict <xulei292@huawei.com>
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