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[UT][PCP&DCP] UT for block_table.py#5032

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wangxiyuan merged 2 commits intovllm-project:mainfrom
pisceskkk:ut
Jan 6, 2026
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[UT][PCP&DCP] UT for block_table.py#5032
wangxiyuan merged 2 commits intovllm-project:mainfrom
pisceskkk:ut

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@pisceskkk pisceskkk commented Dec 15, 2025 •
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Purpose

This PR add unit test for compute_slot_mapping function in block_table.py with various pcp_size & dcp_size & cp_kv_cache_interleave_size.

Test Plan

pytest tests/ut/worker/test_block_table.py

Test Result

==== 3 passed, 2 warnings in 0.20s ====

@pisceskkk
Add unit tests for BlockTable.compute_slot_mapping() with various PCP…
e4b7d4a 
…, DCP, and p_kv_cache_interleave_size

Signed-off-by: QiuChunshuo <qiuchunshuo@huawei.com>
@pisceskkk
lint & clean code
a463634 
Signed-off-by: QiuChunshuo <qiuchunshuo@huawei.com>
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github-actions Bot commented Dec 15, 2025

👋 Hi! Thank you for contributing to the vLLM Ascend project. The following points will speed up your PR merge:‌‌

  • A PR should do only one thing, smaller PRs enable faster reviews.
  • Every PR should include unit tests and end-to-end tests ‌to ensure it works and is not broken by other future PRs.
  • Write the commit message by fulfilling the PR description to help reviewer and future developers understand.

If CI fails, you can run linting and testing checks locally according Contributing and Testing.

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wangxiyuan commented Dec 15, 2025

maybe we'll remove block table file later. Let's wait more. @MengqingCao

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wangxiyuan commented Jan 5, 2026

@MengqingCao do we still need this change?

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MengqingCao commented Jan 6, 2026

@MengqingCao do we still need this change?

I'm removing blocktable in this pr: #5182, but there are some issues with it and I've little time to fix it. maybe we can merge this first to ensure quality.

@wangxiyuan wangxiyuan merged commit e079380 into vllm-project:main Jan 6, 2026
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845473182 pushed a commit to 845473182/vllm-ascend that referenced this pull request Jan 6, 2026
Merge branch 'main' of https://github.com/vllm-project/vllm-ascend in…
3650848 
…to FIA_rebase

* 'main' of https://github.com/vllm-project/vllm-ascend: (58 commits)
  [Main2Main] Upgrade vllm commit to 0106 (vllm-project#5617)
  [CI]update bisheng version (vllm-project#5621)
  [UT][PCP&DCP] UT for block_table.py (vllm-project#5032)
  [Main2Main] Upgrade vllm commit to 0105 (vllm-project#5595)
  [CI] mv ops to correct path (vllm-project#5615)
  [BugFix] Fix Smoke Testing Bug for DSR1 longseq (vllm-project#5613)
  Revert "[Feat] enable hierarchical mc2 ops on A2 by default (vllm-project#5545)" (vllm-project#5611)
  [TRITON][TEST]Add nightly test for triton split_qkv_rmsnorm_rope (vllm-project#5267)
  [perf] Fix MLAPO weight disposal for KV-consumer MLA in PD-mix deploy... (vllm-project#5192)
  [docs] Correct image about prefill phase of PCP (vllm-project#5598)
  [CI] update triton-ascend version (vllm-project#5584)
  [P/D]Remove mooncake kvpool unused parameter `local_hostname` (vllm-project#5574)
  [Bugfix] record cos and sin cache in AscendRotaryEmbedding (vllm-project#5516)
  [bugfix] fix test_camem failed with triton-ascend (vllm-project#5492)
  [UT]add triton ops ut :  test_fused_qkvzba_split_reshape_cat (vllm-project#5474)
  [CI] Download models from ms (vllm-project#5405)
  Docs: Add A3 Docker image guidance for Atlas A3 machines (vllm-project#5256)
  [Doc] Add NNAL installation guide and requirements (vllm-project#5235)
  Add the requirement of arctic-inference which  speculative decoding with suffix_decode  (vllm-project#5045)
  [BugFix][Fusion] Fix graph fusion failure problem (vllm-project#5253)
  ...
Rozwel-dx pushed a commit to Rozwel-dx/vllm-ascend that referenced this pull request Jan 8, 2026
@pisceskkk @Rozwel-dx
[UT][PCP&DCP] UT for block_table.py (vllm-project#5032)
746cce8 
## Purpose
This PR add unit test for `compute_slot_mapping` function in
`block_table.py` with various `pcp_size` & `dcp_size` &
`cp_kv_cache_interleave_size`.

## Test Plan
```
pytest tests/ut/worker/test_block_table.py
```
## Test Result
```
==== 3 passed, 2 warnings in 0.20s ====
```
- vLLM version: v0.12.0
- vLLM main:
vllm-project/vllm@ad32e3e

---------

Signed-off-by: QiuChunshuo <qiuchunshuo@huawei.com>
@pisceskkk pisceskkk deleted the ut branch January 8, 2026 07:12
aipaes pushed a commit to aipaes/vllm-ascend that referenced this pull request Jan 15, 2026
@pisceskkk
[UT][PCP&DCP] UT for block_table.py (vllm-project#5032)
d343e59 
## Purpose
This PR add unit test for `compute_slot_mapping` function in
`block_table.py` with various `pcp_size` & `dcp_size` &
`cp_kv_cache_interleave_size`.

## Test Plan
```
pytest tests/ut/worker/test_block_table.py
```
## Test Result
```
==== 3 passed, 2 warnings in 0.20s ====
```
- vLLM version: v0.12.0
- vLLM main:
vllm-project/vllm@ad32e3e

---------

Signed-off-by: QiuChunshuo <qiuchunshuo@huawei.com>
ZRJ026 pushed a commit to ZRJ026/vllm-ascend that referenced this pull request Feb 28, 2026
@pisceskkk
[UT][PCP&DCP] UT for block_table.py (vllm-project#5032)
d8c740d 
## Purpose
This PR add unit test for `compute_slot_mapping` function in
`block_table.py` with various `pcp_size` & `dcp_size` &
`cp_kv_cache_interleave_size`.

## Test Plan
```
pytest tests/ut/worker/test_block_table.py
```
## Test Result
```
==== 3 passed, 2 warnings in 0.20s ====
```
- vLLM version: v0.12.0
- vLLM main:
vllm-project/vllm@ad32e3e

---------

Signed-off-by: QiuChunshuo <qiuchunshuo@huawei.com>
Signed-off-by: zrj026 <zhangrunjiang026@gmail.com>
maoxx241 pushed a commit to maoxx241/vllm-ascend that referenced this pull request Mar 2, 2026
@pisceskkk @maoxx241
[UT][PCP&DCP] UT for block_table.py (vllm-project#5032)
f9b0156 
## Purpose
This PR add unit test for `compute_slot_mapping` function in
`block_table.py` with various `pcp_size` & `dcp_size` &
`cp_kv_cache_interleave_size`.

## Test Plan
```
pytest tests/ut/worker/test_block_table.py
```
## Test Result
```
==== 3 passed, 2 warnings in 0.20s ====
```
- vLLM version: v0.12.0
- vLLM main:
vllm-project/vllm@ad32e3e

---------

Signed-off-by: QiuChunshuo <qiuchunshuo@huawei.com>
ZRJ026 pushed a commit to ZRJ026/vllm-ascend that referenced this pull request Mar 4, 2026
@pisceskkk
[UT][PCP&DCP] UT for block_table.py (vllm-project#5032)
3aa07b7 
## Purpose
This PR add unit test for `compute_slot_mapping` function in
`block_table.py` with various `pcp_size` & `dcp_size` &
`cp_kv_cache_interleave_size`.

## Test Plan
```
pytest tests/ut/worker/test_block_table.py
```
## Test Result
```
==== 3 passed, 2 warnings in 0.20s ====
```
- vLLM version: v0.12.0
- vLLM main:
vllm-project/vllm@ad32e3e

---------

Signed-off-by: QiuChunshuo <qiuchunshuo@huawei.com>
Signed-off-by: zrj026 <zhangrunjiang026@gmail.com>
LCAIZJ pushed a commit to LCAIZJ/vllm-ascend that referenced this pull request Mar 7, 2026
@pisceskkk @LCAIZJ
[UT][PCP&DCP] UT for block_table.py (vllm-project#5032)
3028c65 
## Purpose
This PR add unit test for `compute_slot_mapping` function in
`block_table.py` with various `pcp_size` & `dcp_size` &
`cp_kv_cache_interleave_size`.

## Test Plan
```
pytest tests/ut/worker/test_block_table.py
```
## Test Result
```
==== 3 passed, 2 warnings in 0.20s ====
```
- vLLM version: v0.12.0
- vLLM main:
vllm-project/vllm@ad32e3e

---------

Signed-off-by: QiuChunshuo <qiuchunshuo@huawei.com>
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