[AMD] Enable InThreadTranspose pass for RDNA3 / RDNA3.5 (gfx110x/115x)

[mgehre-amd]

InThreadTranspose rewrites tt.load -> ttg.local_alloc -> ttg.local_load -> dot_op so the K-contiguous WMMA/MFMA operand can be
read from LDS as wide ds_load_b128 instead of scalar ds_load_u16
pairs when the load order doesn't match the consumer's K dimension.
The pattern matcher in matchInThreadTransposePattern already accepts
AMDWmmaEncodingAttr alongside AMDMfmaEncodingAttr, but the gate in
is_in_thread_transpose_enabled only activates the pass on gfx942
(CDNA3) and gfx120x (RDNA4, enabled in #10185). Extend it to also
cover RDNA3 (gfx110x/gfx1103) and RDNA3.5 (gfx115x).

Added a inThreadTranspose_wmma sub-test to
test/TritonGPU/amd/in-thread-transpose.mlir (gfx1151, wave32, WMMA
encoding) that verifies the pass produces an amdg.in_thread_transpose
op and that the downstream ttg.local_load returns the K-contiguous
dot_op layout (kWidth = 16).

On AITER's flash_attn_2.varlen_fwd at the Qwen3-Omni ViT prefill
shape (B=1, S=3200, H=16, head_dim=72, fp16) on gfx1151, this lifts
the inner-loop V local_load from 512 scalar ds_load_u16(_d16_hi)
to 144 vectorized ds_load_b128 and gives a 3.8% median speedup
(3.042 -> 2.925 ms). Stacked with #10389 (D8 int
specialization), the same kernel reaches 2.376 ms (-21.9% vs main).

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