[AMD] Enable IN_THREAD_TRANSPOSE to GFX1201 by default #10185
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antiagainst
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Apr 30, 2026
| def is_in_thread_transpose_enabled(arch): | ||
| return (arch == "gfx942") if knobs.amd.use_in_thread_transpose is None else knobs.amd.use_in_thread_transpose | ||
| return (arch in ("gfx942", | ||
| "gfx1201")) if knobs.amd.use_in_thread_transpose is None else knobs.amd.use_in_thread_transpose |
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We should include other gfx12 targets too. See how is_hip_rdna4 defined.
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May 1, 2026
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#10390) `InThreadTranspose` rewrites `tt.load -> ttg.local_alloc -> ttg.local_load -> dot_op` so the K-contiguous WMMA/MFMA operand can be read from LDS as wide `ds_load_b128` instead of scalar `ds_load_u16` pairs when the load order doesn't match the consumer's K dimension. The pattern matcher in `matchInThreadTransposePattern` already accepts `AMDWmmaEncodingAttr` alongside `AMDMfmaEncodingAttr`, but the gate in `is_in_thread_transpose_enabled` only activates the pass on gfx942 (CDNA3) and gfx120x (RDNA4, enabled in #10185). Extend it to also cover RDNA3 (gfx110x/gfx1103) and RDNA3.5 (gfx115x). Added a `inThreadTranspose_wmma` sub-test to `test/TritonGPU/amd/in-thread-transpose.mlir` (gfx1151, wave32, WMMA encoding) that verifies the pass produces an `amdg.in_thread_transpose` op and that the downstream `ttg.local_load` returns the K-contiguous `dot_op` layout (`kWidth = 16`). On AITER's `flash_attn_2.varlen_fwd` at the Qwen3-Omni ViT prefill shape (B=1, S=3200, H=16, head_dim=72, fp16) on gfx1151, this lifts the inner-loop V `local_load` from 512 scalar `ds_load_u16(_d16_hi)` to 144 vectorized `ds_load_b128` and gives a 3.8% median speedup (3.042 -> 2.925 ms).
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Enables in-thread transpose on by default for gfx1201, matching the existing default for gfx942. It will transpose
the elements within a thread using registers after global load and before local write in order to maintain good global memory coalescing and wide ds instruction bitwidth and avoid shared memory bank conflicts.
Flash-Attention 2 Results (bf16):
GEMM Results (bf16)
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