"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
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Jul 9, 2023 - Verilog
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vlsi-design
Here are 65 public repositories matching this topic...
Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
rtl verilog fulladder vlsi multiplier hardware-description-language wallace vlsi-design vlsi-project dadda-tree carry-save-adder fast-multiplication dadda-multiplier tree-multipliers
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Jun 6, 2024 - Verilog
Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.
signal-processing fast-fourier-transform digital-signal-processing vlsi-physical-design fpga-accelerator vlsi-design vlsi-project
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May 20, 2020 - Verilog
Microshift Compression: An Efficient Image Compression Algorithm for Hardware
fpga matlab image-processing hardware-architectures verilog image-compression computational-photography image-sensor low-power vlsi-design hdlcoder smart-image-sensor
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Apr 21, 2021 - Verilog
This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out
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Jan 23, 2024 - Verilog
The Repository contains the code of various Digital Circuits
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Aug 7, 2023 - Verilog
This is part of EC383 - Mini Project in VLSI Design.
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May 8, 2022 - Verilog
UART - RTL Design and Verification
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Sep 6, 2021 - Verilog
"Mastering RTL-Coding : From Fundamentals to Advanced Programming Techniques using Verilog,System Verilog and UVM"
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Mar 10, 2025 - Verilog
This project proposes to demonstrate the capabilities and scope of Verilog HDL by implementing the control system of an automatic washing machine. The above mentioned objective by implementing the Control System of an automatic washing using the Finite State Machine model. The washing machine control system generates all the control signals requ…
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Sep 6, 2021 - Verilog
VLSI Design - Spring 2022
university solution lab cse brac brac-university vlsi-design solves bracu cse460 bracucse460 bracucse lab-solutions lab-solves
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Mar 15, 2022 - Verilog
Learning Path: RISC-V System-on-Chip (SoC) design, from Register Transfer Level (RTL) to a GDSII layout | Complete VLSI design flow using open-source EDA tools.
opensource magic asic rtl icarus-verilog gtkwave yosys risc-v klayout ngspice vlsi-design asic-design openlane gdsii-flow system-on-chip-design
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Oct 24, 2025 - Verilog
Design of real time clock(RTC) using Verilog HDL
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Dec 5, 2021 - Verilog
I've delved into leveraging my academic prowess to drive projects that contribute to my career advancement.
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Apr 8, 2025 - Verilog
THIS REPOSITORY CONTAINS DESIGN FILES FOR SPI TO 32 DIGITAL IO EXPANSION MODULE
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Nov 6, 2021 - Verilog
TicTacToe game using verilog hdl and implementation in spartan-3 FPGA board
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Feb 3, 2022 - Verilog
Verilog practice sessions by Mr. Sujit Panda
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May 11, 2025 - Verilog
Universal Shift Register is a register which can be configured to load and/or retrieve the data in any mode (either serial or parallel) by shifting it either towards right or towards left. In other words, a combined design of unidirectional (either right- or left-shift of data bits as in case of SISO, SIPO, PISO, PIPO) and bidirectional shift re…
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Jul 25, 2021 - Verilog
A robust digital design for implementing a floating-point ALU following up ASIC Frontend and Backend flow with hardware layout optimization using Openlane
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Dec 25, 2024 - Verilog
ALU (Arithmetic and Logic Unit), Ripple carry adder, Half adder and full adder are designed using all 3 styles (structural, behavioral, dataflow) and tested by generating stimulus using testbench
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Mar 27, 2023 - Verilog
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