
Hi there!
Digital electronics, FPGAs, multi-gigabit interfaces
- Saint-Petersburg, Russia
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vivado_design_space_explorer_template
vivado_design_space_explorer_template PublicIterative compilation and reporting scripts for AMD / Xilinx Vivado
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xilinx_max_power
xilinx_max_power PublicStress test power subsystem of your Xilinx FPGA board
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quartus_design_space_explorer_template
quartus_design_space_explorer_template PublicIterative compilation and reporting scripts for Intel / Altera Quartus
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avr_assembler_macros
avr_assembler_macros PublicCollection of assembler macros for Atmel AVR microcontroller
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altium_designer_settings_and_preferences
altium_designer_settings_and_preferences PublicTemplates, settings and preferences to use with Altium Designer
51 contributions in the last year
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Activity overview
Contributed to
kaxap/arl,
pConst/basic_verilog,
pConst/opencores.org_verilog_vhdl_ip_cores_flat
and 5 other
repositories
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Contribution activity
April 2025
Created 1 commit in 1 repository
Opened 1 pull request in 1 repository
kaxap/arl
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Update 20250426
This contribution was made on Apr 27