A completely functional encryption decryption model with specially generated Asymmetric key verification
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Updated
Jan 30, 2018 - Verilog
A completely functional encryption decryption model with specially generated Asymmetric key verification
This is a simple FIFO queue implementation in Verilog for the Modern Computer Architectures course (2016-2017) of Harokopio University.
Quickstart guide on Icarus Verilog.
A simple up-down counter project made using icarus verilog as a part of the Digital Design and Computer Organization course (UE19CS207) at PES University.
16-bit DADDA Multiplier design using using 5:2 compressor as the major reduction compressor and 4:2 compressor; and FullAdder and HalfAdder to simulate 3:2 and 2:2 compressors respectively.
Simple 8-bit single-cycle processor which includes an ALU, a register file and control logic, using Verilog HDL
This project provide the necessary to run a env test a simple uart verilog using SystemC and running it on icarus verilog
A place to keep my synthesizable verilog examples.
Laboratory Mini Project for the Course - Digital Design and Computer Organization (UE22CS251A)
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