16-bit DADDA Multiplier design using using 5:2 compressor as the major reduction compressor and 4:2 compressor; FullAdder and HalfAdder to simulate 3:2 and 2:2 compressors respectively.
iverilog dadda_tb.v
-Test Bench
-GTK Waveform
-
Notifications
You must be signed in to change notification settings - Fork 0
16-bit DADDA Multiplier design using using 5:2 compressor as the major reduction compressor and 4:2 compressor; and FullAdder and HalfAdder to simulate 3:2 and 2:2 compressors respectively.
License
arjunrajasekharan/16-bit-DADDA-Multiplier
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
Folders and files
| Name | Name | Last commit message | Last commit date | |
|---|---|---|---|---|
Repository files navigation
About
16-bit DADDA Multiplier design using using 5:2 compressor as the major reduction compressor and 4:2 compressor; and FullAdder and HalfAdder to simulate 3:2 and 2:2 compressors respectively.
Topics
Resources
License
Stars
Watchers
Forks
Releases
No releases published