gtkwave
Here are 29 public repositories matching this topic...
Laboratory Mini Project for the Course - Digital Design and Computer Organization (UE22CS251A)
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Dec 22, 2023 - Verilog
This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog
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Mar 22, 2024 - Verilog
This is a simple FIFO queue implementation in Verilog for the Modern Computer Architectures course (2016-2017) of Harokopio University.
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Jun 16, 2018 - Verilog
Simple 8-bit single-cycle processor which includes an ALU, a register file and control logic, using Verilog HDL
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Jul 8, 2022 - Verilog
Practice Codes of Verilog Language
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Apr 1, 2024 - Verilog
Developing different projects in order to understand how the Icarus Verilog tools work with GTKWave and Yosys.
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Jul 3, 2024 - Verilog
A simple up-down counter project made using icarus verilog as a part of the Digital Design and Computer Organization course (UE19CS207) at PES University.
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Dec 6, 2020 - Verilog
Hardware Design Program Hosting By VLSI System Design (https://www.vlsisystemdesign.com/)
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May 8, 2024 - Verilog
This repository contains an implementation of a RV32I fetch pipeline microprocessor. The RV32I is a 32-bit RISC-V instruction set architecture, with the 'I' extension indicating the base integer instructions.
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Apr 11, 2024 - Verilog
16-bit DADDA Multiplier design using using 5:2 compressor as the major reduction compressor and 4:2 compressor; and FullAdder and HalfAdder to simulate 3:2 and 2:2 compressors respectively.
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May 14, 2021 - Verilog
Provide a basic structure to starts a Verilog project. Create a Verilog Design Flow based on Makefiles, Iverilog, GTKwave. Create a VS Code environment with Linting (verilator and verible), formatting and Language Server (verible)
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Apr 26, 2024 - Verilog
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