🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

A Forth CPU and System on a Chip, based on the J1, written in VHDL

Basic RISC-V CPU implementation in VHDL.

A bit-serial CPU written in VHDL, with a simulator written in C.

A computer (FPGA SoC) based on the MRISC32-A1 CPU

A re-creation of a Cosmac ELF computer, Coded in SpinalHDL

VHDL project to run a simple 8-bit computer very similar to the one built by Ben Eater (see https://eater.net)

Simple SoC in VHDL with full toolchain and custom board.

A user-expandable micro-computer system that runs on an FPGA development board and includes the FORTH software language. The system is currently hosted on the Digilent Nexys 4 and Nexys 4 DDR

A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )

A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA

CPU and home computer project

Custom 64-bit pipelined RISC processor

Design and implementation of a complete ARM based CPU.

FISC - Flexible Instruction Set Computer - Is the new Instruction Set Architecture inspired by ARMv8 and x86-64

基于LoongArch32/MIPS32指令集的七级流水线CPU。NSCSCC（龙芯杯）2023参赛作品。

💻 Simulation for the architecture of a processor inspired by the ideas of PDP-11 processor

SAYEH cpu-memory basic computer

Dual-core 16-bit RISC processor

Extension version of TinyMIPS processor, which is an implementation of for USTB computer composition principle course design.