[sim] rework default testbench

[stnolting]

Triggered by @mahdi259 in #1115 this PR adds new generics to the default testbench that control implementation (and initialization) of two processor-external memories.

-- external memory A --
EXT_MEM_A_EN   : boolean                        := true;        -- enable memory
EXT_MEM_A_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address, has to be word-aligned
EXT_MEM_A_SIZE : natural                        := 64;          -- memory size in bytes, min 4
EXT_MEM_A_FILE : string                         := "";          -- memory initialization file (plain HEX), no initialization if empty
-- external memory B --
EXT_MEM_B_EN   : boolean                        := true;        -- enable memory
EXT_MEM_B_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address, has to be word-aligned
EXT_MEM_B_SIZE : natural                        := 64;          -- memory size in bytes, min 4
EXT_MEM_B_FILE : string                         := ""           -- memory initialization file (plain HEX), no initialization if empty

[mahdi259]

1- Should we give path of the hex files to EXT_MEM_A_FILE and EXT_MEM_B_FILE? (Could you fill the paths to give an example)

2- Both of Instructions and data are merged into one hex file after compilation, so dmem initialization is done by processor through copying data from imem to dmem. Is it true?

[stnolting]

1- Should we give path of the hex files to EXT_MEM_A_FILE and EXT_MEM_B_FILE? (Could you fill the paths to give an example)

Sure!

First of all, compile a program using the hex target:

neorv32/sw/example/hello_world$ make USER_FLAGS+=-DUART0_SIM_MODE clean hex
../../../sw/lib/source/neorv32_uart.c: In function 'neorv32_uart_setup':
../../../sw/lib/source/neorv32_uart.c:109:2: warning: #warning UART0_SIM_MODE (primary UART) enabled! Sending all UART0.TX data to text.io simulation output instead of real UART0 transmitter. Use this for simulation only! [-Wcpp]
  109 | #warning UART0_SIM_MODE (primary UART) enabled! Sending all UART0.TX data to text.io simulation output instead of real UART0 transmitter. Use this for simulation only!
      |  ^~~~~~~
Memory utilization:
   text    data     bss     dec     hex filename
   5532       0     116    5648    1610 main.elf
Generating neorv32_raw_exe.hex

(I am using USER_FLAGS+=-DUART0_SIM_MODE to get faster UART output during simulation)

Then you can pass neorv32_exe.hex to the testbench. The files provided by the accoding generics have to be absolute or relative to the simulator's simulation folder. If you use the build-in GHDL setup, the simulation folder is sim.

For the GHDL configuration you can do all the genric configuration within the command line:

neorv32/sw/example/hello_world$ make GHDL_RUN_FLAGS+="-gBOOT_MODE_SELECT=1 -gMEM_INT_IMEM_EN=false -gEXT_MEM_A_EN=true -gEXT_MEM_A_SIZE=8192 -gEXT_MEM_A_FILE=../sw/example/hello_world/neorv32_raw_exe.hex" sim
Generating neorv32_application_image.vhd
Installing application image to ../../../rtl/core/neorv32_application_image.vhd
Simulating processor using default testbench...
[TIP] Compile application with USER_FLAGS+=-DUART[0/1]_SIM_MODE to enable UART[0/1]'s simulation mode (redirect UART output to simulator console).
GHDL simulation run parameters: -gBOOT_MODE_SELECT=1 -gMEM_INT_IMEM_EN=false -gEXT_MEM_A_EN=true -gEXT_MEM_A_SIZE=8192 -gEXT_MEM_A_FILE=../sw/example/hello_world/neorv32_raw_exe.hex
../rtl/core/neorv32_top.vhd:343:5:@0ms:(assertion note): [NEORV32] The NEORV32 RISC-V Processor (v1.10.7.2), github.com/stnolting/neorv32
../rtl/core/neorv32_top.vhd:349:5:@0ms:(assertion note): [NEORV32] Processor Configuration: CPU DMEM I-CACHE D-CACHE XBUS XBUS-CACHE XIP XIP-CACHE GPIO MTIME UART0 UART1 SPI SDI TWI PWM WDT TRNG CFS NEOLED XIRQ GPTMR ONEWIRE DMA SLINK CRC SYSINFO OCD-AUTH
../rtl/core/neorv32_top.vhd:401:5:@0ms:(assertion note): [NEORV32] BOOT_MODE_SELECT = 1: booting from custom address
../rtl/core/neorv32_clockgate.vhd:38:3:@0ms:(assertion warning): [NEORV32] Clock gating enabled (using default/generic clock switch).
../rtl/core/neorv32_cpu.vhd:136:3:@0ms:(assertion note): [NEORV32] CPU ISA: rv32ibmux_zalrsc_zba_zbb_zbkb_zbkc_zbkx_zbs_zicntr_zicond_zicsr_zifencei_zihpm_zfinx_zkn_zknd_zkne_zknh_zks_zksed_zksh_zkt_zmmul_zxcfu_sdext_sdtrig_smpmp
../rtl/core/neorv32_cpu.vhd:172:3:@0ms:(assertion note): [NEORV32] CPU tuning options: fast_mul fast_shift rf_hw_rst
../rtl/core/neorv32_cpu.vhd:179:3:@0ms:(assertion warning): [NEORV32] Assuming this is a simulation.
../rtl/core/neorv32_trng.vhd:295:3:@0ms:(assertion note): [neoTRNG] The neoTRNG (v3.2) - A Tiny and Platform-Independent True Random Number Generator, https://github.com/stnolting/neoTRNG
../rtl/core/neorv32_trng.vhd:302:3:@0ms:(assertion warning): [neoTRNG] Simulation-mode enabled (NO TRUE/PHYSICAL RANDOM)!
../rtl/core/neorv32_debug_auth.vhd:48:3:@0ms:(assertion warning): [NEORV32] using DEFAULT on-chip debugger authenticator. Replace by custom module.

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Hello world! :)

Here, I am using the external memory A. Make sure to adjust the size according to the compilation outputs.

2- Both of Instructions and data are merged into one hex file after compilation, so dmem initialization is done by processor through copying data from imem to dmem. Is it true?

Yes, at least if you compile an executable. But you could also generate a HEX file that contains only some data, put that into one of the external memories and use that from another HEX file that includes the actual executable.