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[sim] rework default testbench (#1119)
2 parents 64d7699 + 9114f10 commit 79e9df2

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6 files changed

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-82
lines changed

6 files changed

+177
-82
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‎CHANGELOG.md

+1
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12
2929

3030
| Date | Version | Comment | Ticket |
3131
|:----:|:-------:|:--------|:------:|
32+
| 12.12.2024 | 1.10.7.2 | add external memory configuration/initialization options to testbench | [#1119](https://github.com/stnolting/neorv32/pull/1119) |
3233
| 11.12.2024 | 1.10.7.1 | :test_tube: shrink bootloader's minimal ISA (`rv32e`) and RAM (256 bytes) requirements | [#1118](https://github.com/stnolting/neorv32/pull/1118) |
3334
| 10.12.2024 | [**:rocket:1.10.7**](https://github.com/stnolting/neorv32/releases/tag/v1.10.7) | **New release** | |
3435
| 03.12.2024 | 1.10.6.9 | :sparkles: add ONEWIRE command and data FIFO; :warning: rework ONEWIRE interface register layout; :bug: fix regression: busy flag was stuck at zero | [#1113](https://github.com/stnolting/neorv32/pull/1113) |

‎rtl/core/neorv32_package.vhd

+12-1
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@ package neorv32_package is
2929

3030
-- Architecture Constants -----------------------------------------------------------------
3131
-- -------------------------------------------------------------------------------------------
32-
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100701"; -- hardware version
32+
constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100702"; -- hardware version
3333
constant archid_c : natural := 19; -- official RISC-V architecture ID
3434
constant XLEN : natural := 32; -- native data path width
3535

@@ -194,6 +194,17 @@ package neorv32_package is
194194
cyc : std_ulogic; -- valid cycle
195195
end record;
196196

197+
-- source (request) termination --
198+
constant xbus_req_terminate_c : xbus_req_t := (
199+
addr => (others => '0'),
200+
data => (others => '0'),
201+
tag => (others => '0'),
202+
we => '0',
203+
sel => (others => '0'),
204+
stb => '0',
205+
cyc => '0'
206+
);
207+
197208
-- xbus response --
198209
type xbus_rsp_t is record
199210
data : std_ulogic_vector(31 downto 0); -- read data, valid if ack=1

‎sim/neorv32_tb.vhd

+77-46
Original file line numberDiff line numberDiff line change
@@ -18,8 +18,10 @@ use neorv32.neorv32_package.all;
1818

1919
entity neorv32_tb is
2020
generic (
21+
-- processor --
2122
CLOCK_FREQUENCY : natural := 100_000_000; -- clock frequency of clk_i in Hz
2223
BOOT_MODE_SELECT : natural range 0 to 2 := 2; -- boot from pre-initialized IMEM
24+
BOOT_ADDR_CUSTOM : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CPU boot address (if boot_config = 1)
2325
RISCV_ISA_C : boolean := false; -- implement compressed extension
2426
RISCV_ISA_E : boolean := false; -- implement embedded RF extension
2527
RISCV_ISA_M : boolean := true; -- implement mul/div extension
@@ -54,7 +56,17 @@ entity neorv32_tb is
5456
ICACHE_BLOCK_SIZE : natural range 4 to 2**16 := 32; -- i-cache: block size in bytes (min 4), has to be a power of 2
5557
DCACHE_EN : boolean := true; -- implement data cache
5658
DCACHE_NUM_BLOCKS : natural range 1 to 256 := 32; -- d-cache: number of blocks (min 1), has to be a power of 2
57-
DCACHE_BLOCK_SIZE : natural range 4 to 2**16 := 32 -- d-cache: block size in bytes (min 4), has to be a power of 2
59+
DCACHE_BLOCK_SIZE : natural range 4 to 2**16 := 32; -- d-cache: block size in bytes (min 4), has to be a power of 2
60+
-- external memory A --
61+
EXT_MEM_A_EN : boolean := false; -- enable memory
62+
EXT_MEM_A_BASE : std_ulogic_vector(31 downto 0) := x"00000000"; -- base address, has to be word-aligned
63+
EXT_MEM_A_SIZE : natural := 64; -- memory size in bytes, min 4
64+
EXT_MEM_A_FILE : string := ""; -- memory initialization file (plain HEX), no initialization if empty
65+
-- external memory B --
66+
EXT_MEM_B_EN : boolean := false; -- enable memory
67+
EXT_MEM_B_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- base address, has to be word-aligned
68+
EXT_MEM_B_SIZE : natural := 64; -- memory size in bytes, min 4
69+
EXT_MEM_B_FILE : string := "" -- memory initialization file (plain HEX), no initialization if empty
5870
);
5971
end neorv32_tb;
6072

@@ -79,8 +91,8 @@ architecture neorv32_tb_rtl of neorv32_tb is
7991
signal slink_tx, slink_rx : slink_t;
8092

8193
-- XBUS (Wishbone b4) bus --
82-
signal xbus_core_req, xbus_imem_req, xbus_dmem_req, xbus_mmio_req, xbus_trig_req : xbus_req_t;
83-
signal xbus_core_rsp, xbus_imem_rsp, xbus_dmem_rsp, xbus_mmio_rsp, xbus_trig_rsp : xbus_rsp_t;
94+
signal xbus_core_req, xbus_ext_mem_a_req, xbus_ext_mem_b_req, xbus_mmio_req, xbus_trig_req : xbus_req_t;
95+
signal xbus_core_rsp, xbus_ext_mem_a_rsp, xbus_ext_mem_b_rsp, xbus_mmio_rsp, xbus_trig_rsp : xbus_rsp_t;
8496

8597
begin
8698

@@ -102,7 +114,7 @@ begin
102114
JEDEC_ID => "00000000000",
103115
-- Boot Configuration --
104116
BOOT_MODE_SELECT => BOOT_MODE_SELECT,
105-
BOOT_ADDR_CUSTOM => x"00000000",
117+
BOOT_ADDR_CUSTOM => BOOT_ADDR_CUSTOM,
106118
-- On-Chip Debugger (OCD) --
107119
OCD_EN => true,
108120
OCD_AUTHENTICATION => true,
@@ -142,7 +154,7 @@ begin
142154
HPM_NUM_CNTS => 12,
143155
HPM_CNT_WIDTH => 40,
144156
-- Internal Instruction memory --
145-
MEM_INT_IMEM_EN => MEM_INT_IMEM_EN ,
157+
MEM_INT_IMEM_EN => MEM_INT_IMEM_EN,
146158
MEM_INT_IMEM_SIZE => MEM_INT_IMEM_SIZE,
147159
-- Internal Data memory --
148160
MEM_INT_DMEM_EN => MEM_INT_DMEM_EN,
@@ -352,9 +364,9 @@ begin
352364
-- -------------------------------------------------------------------------------------------
353365
sim_rx_uart0: entity work.sim_uart_rx
354366
generic map (
355-
name => "uart0",
356-
fclk => real(CLOCK_FREQUENCY),
357-
baud => real(19200)
367+
NAME => "uart0",
368+
FCLK => real(CLOCK_FREQUENCY),
369+
BAUD => real(19200)
358370
)
359371
port map (
360372
clk => clk_gen,
@@ -363,9 +375,9 @@ begin
363375

364376
sim_rx_uart1: entity work.sim_uart_rx
365377
generic map (
366-
name => "uart1",
367-
fclk => real(CLOCK_FREQUENCY),
368-
baud => real(19200)
378+
NAME => "uart1",
379+
FCLK => real(CLOCK_FREQUENCY),
380+
BAUD => real(19200)
369381
)
370382
port map (
371383
clk => clk_gen,
@@ -378,59 +390,78 @@ begin
378390
xbus_interconnect: entity work.xbus_gateway
379391
generic map (
380392
-- device address size in bytes and base address --
381-
DEV_0_SIZE => MEM_INT_IMEM_SIZE, DEV_0_BASE => mem_imem_base_c,
382-
DEV_1_SIZE => MEM_INT_DMEM_SIZE, DEV_1_BASE => mem_dmem_base_c,
383-
DEV_2_SIZE => 64, DEV_2_BASE => x"F0000000",
384-
DEV_3_SIZE => 4, DEV_3_BASE => x"FF000000"
393+
DEV_0_EN => EXT_MEM_A_EN, DEV_0_SIZE => EXT_MEM_A_SIZE, DEV_0_BASE => EXT_MEM_A_BASE,
394+
DEV_1_EN => EXT_MEM_B_EN, DEV_1_SIZE => EXT_MEM_B_SIZE, DEV_1_BASE => EXT_MEM_B_BASE,
395+
DEV_2_EN => true, DEV_2_SIZE => 64, DEV_2_BASE => x"F0000000",
396+
DEV_3_EN => true, DEV_3_SIZE => 4, DEV_3_BASE => x"FF000000"
385397
)
386398
port map (
387399
-- host port --
388400
host_req_i => xbus_core_req,
389401
host_rsp_o => xbus_core_rsp,
390402
-- device ports --
391-
dev_0_req_o => xbus_imem_req, dev_0_rsp_i => xbus_imem_rsp,
392-
dev_1_req_o => xbus_dmem_req, dev_1_rsp_i => xbus_dmem_rsp,
393-
dev_2_req_o => xbus_mmio_req, dev_2_rsp_i => xbus_mmio_rsp,
394-
dev_3_req_o => xbus_trig_req, dev_3_rsp_i => xbus_trig_rsp
403+
dev_0_req_o => xbus_ext_mem_a_req, dev_0_rsp_i => xbus_ext_mem_a_rsp,
404+
dev_1_req_o => xbus_ext_mem_b_req, dev_1_rsp_i => xbus_ext_mem_b_rsp,
405+
dev_2_req_o => xbus_mmio_req, dev_2_rsp_i => xbus_mmio_rsp,
406+
dev_3_req_o => xbus_trig_req, dev_3_rsp_i => xbus_trig_rsp
395407
);
396408

397409

398-
-- XBUS: Instruction Memory ---------------------------------------------------------------
410+
-- XBUS: External Memory A ----------------------------------------------------------------
399411
-- -------------------------------------------------------------------------------------------
400-
xbus_imem: entity work.xbus_memory
401-
generic map (
402-
MEM_SIZE => MEM_INT_IMEM_SIZE,
403-
MEM_LATE => 1
404-
)
405-
port map (
406-
clk_i => clk_gen,
407-
rstn_i => rst_gen,
408-
xbus_req_i => xbus_imem_req,
409-
xbus_rsp_o => xbus_imem_rsp
410-
);
411-
412-
413-
-- XBUS: Data Memory ----------------------------------------------------------------------
412+
xbus_external_memory_a_enable:
413+
if EXT_MEM_A_EN generate
414+
xbus_external_memory_a: entity work.xbus_memory
415+
generic map (
416+
MEM_SIZE => EXT_MEM_A_SIZE,
417+
MEM_LATE => 1,
418+
MEM_FILE => EXT_MEM_A_FILE
419+
)
420+
port map (
421+
clk_i => clk_gen,
422+
rstn_i => rst_gen,
423+
xbus_req_i => xbus_ext_mem_a_req,
424+
xbus_rsp_o => xbus_ext_mem_a_rsp
425+
);
426+
end generate;
427+
428+
xbus_external_memory_a_disable:
429+
if not EXT_MEM_A_EN generate
430+
xbus_ext_mem_a_rsp <= xbus_rsp_terminate_c;
431+
end generate;
432+
433+
434+
-- XBUS: External Memory B ----------------------------------------------------------------
414435
-- -------------------------------------------------------------------------------------------
415-
xbus_dmem: entity work.xbus_memory
416-
generic map (
417-
MEM_SIZE => MEM_INT_DMEM_SIZE,
418-
MEM_LATE => 1
419-
)
420-
port map (
421-
clk_i => clk_gen,
422-
rstn_i => rst_gen,
423-
xbus_req_i => xbus_dmem_req,
424-
xbus_rsp_o => xbus_dmem_rsp
425-
);
436+
xbus_external_memory_b_enable:
437+
if EXT_MEM_B_EN generate
438+
xbus_external_memory_b: entity work.xbus_memory
439+
generic map (
440+
MEM_SIZE => EXT_MEM_B_SIZE,
441+
MEM_LATE => 1,
442+
MEM_FILE => EXT_MEM_B_FILE
443+
)
444+
port map (
445+
clk_i => clk_gen,
446+
rstn_i => rst_gen,
447+
xbus_req_i => xbus_ext_mem_b_req,
448+
xbus_rsp_o => xbus_ext_mem_b_rsp
449+
);
450+
end generate;
451+
452+
xbus_external_memory_b_disable:
453+
if not EXT_MEM_B_EN generate
454+
xbus_ext_mem_b_rsp <= xbus_rsp_terminate_c;
455+
end generate;
426456

427457

428458
-- XBUS: Memory-Mapped IO -----------------------------------------------------------------
429459
-- -------------------------------------------------------------------------------------------
430460
xbus_mmio: entity work.xbus_memory
431461
generic map (
432462
MEM_SIZE => 64,
433-
MEM_LATE => 32
463+
MEM_LATE => 32,
464+
MEM_FILE => "" -- no initialization
434465
)
435466
port map (
436467
clk_i => clk_gen,

‎sim/sim_uart_rx.vhd

+7-7
Original file line numberDiff line numberDiff line change
@@ -16,9 +16,9 @@ use std.textio.all;
1616

1717
entity sim_uart_rx is
1818
generic (
19-
name : string; -- receiver name (for log file)
20-
fclk : real; -- clock speed of clk_i in Hz
21-
baud : real -- baud rate
19+
NAME : string; -- receiver name (for log file)
20+
FCLK : real; -- clock speed of clk_i in Hz
21+
BAUD : real -- baud rate
2222
);
2323
port (
2424
clk : in std_ulogic; -- global clock
@@ -33,8 +33,8 @@ architecture sim_uart_rx_rtl of sim_uart_rx is
3333
signal sreg : std_ulogic_vector(8 downto 0) := (others => '0');
3434
signal baudcnt : real;
3535
signal bitcnt : natural;
36-
constant baud_val_c : real := fclk / baud;
37-
file file_out : text open write_mode is "neorv32_tb." & name & "_rx.out";
36+
constant baud_val_c : real := FCLK / BAUD;
37+
file file_out : text open write_mode is "neorv32_tb." & NAME & "_rx.out";
3838

3939
begin
4040

@@ -67,9 +67,9 @@ begin
6767
c := to_integer(unsigned(sreg(8 downto 1)));
6868

6969
if (c < 32) or (c > 32+95) then -- non-printable character?
70-
report name & ".rx: (" & integer'image(c) & ")";
70+
report NAME & ".rx: (" & integer'image(c) & ")";
7171
else
72-
report name & ".rx: " & character'val(c);
72+
report NAME & ".rx: " & character'val(c);
7373
end if;
7474

7575
if (c = 10) then -- LF line break

‎sim/xbus_gateway.vhd

+15-10
Original file line numberDiff line numberDiff line change
@@ -17,11 +17,11 @@ use neorv32.neorv32_package.all;
1717

1818
entity xbus_gateway is
1919
generic (
20-
-- device address size in bytes and base address --
21-
DEV_0_SIZE : natural := 0; DEV_0_BASE : std_ulogic_vector(31 downto 0) := (others => '0');
22-
DEV_1_SIZE : natural := 0; DEV_1_BASE : std_ulogic_vector(31 downto 0) := (others => '0');
23-
DEV_2_SIZE : natural := 0; DEV_2_BASE : std_ulogic_vector(31 downto 0) := (others => '0');
24-
DEV_3_SIZE : natural := 0; DEV_3_BASE : std_ulogic_vector(31 downto 0) := (others => '0')
20+
-- device enable, address size in bytes and base address (word-aligned) --
21+
DEV_0_EN : boolean := false; DEV_0_SIZE : natural := 0; DEV_0_BASE : std_ulogic_vector(31 downto 0) := (others => '0');
22+
DEV_1_EN : boolean := false; DEV_1_SIZE : natural := 0; DEV_1_BASE : std_ulogic_vector(31 downto 0) := (others => '0');
23+
DEV_2_EN : boolean := false; DEV_2_SIZE : natural := 0; DEV_2_BASE : std_ulogic_vector(31 downto 0) := (others => '0');
24+
DEV_3_EN : boolean := false; DEV_3_SIZE : natural := 0; DEV_3_BASE : std_ulogic_vector(31 downto 0) := (others => '0')
2525
);
2626
port (
2727
-- host port --
@@ -41,8 +41,10 @@ architecture xbus_gateway_rtl of xbus_gateway is
4141
constant num_devs_c : natural := 4; -- number of device ports
4242

4343
-- list of device base address and address size --
44+
type dev_en_list_t is array (0 to num_devs_c-1) of boolean;
4445
type dev_base_list_t is array (0 to num_devs_c-1) of std_ulogic_vector(31 downto 0);
4546
type dev_size_list_t is array (0 to num_devs_c-1) of natural;
47+
constant dev_en_list_c : dev_en_list_t := (DEV_0_EN, DEV_1_EN, DEV_2_EN, DEV_3_EN);
4648
constant dev_base_list_c : dev_base_list_t := (DEV_0_BASE, DEV_1_BASE, DEV_2_BASE, DEV_3_BASE);
4749
constant dev_size_list_c : dev_size_list_t := (DEV_0_SIZE, DEV_1_SIZE, DEV_2_SIZE, DEV_3_SIZE);
4850

@@ -66,7 +68,7 @@ begin
6668
-- device select --
6769
acc_en_gen:
6870
for i in 0 to num_devs_c-1 generate
69-
acc_en(i) <= '1' when (dev_size_list_c(i) > 0) and
71+
acc_en(i) <= '1' when (dev_size_list_c(i) > 0) and dev_en_list_c(i) and
7072
(unsigned(host_req_i.addr) >= unsigned(dev_base_list_c(i))) and
7173
(unsigned(host_req_i.addr) < (unsigned(dev_base_list_c(i)) + dev_size_list_c(i))) else '0';
7274
end generate;
@@ -76,9 +78,12 @@ begin
7678
for i in 0 to num_devs_c-1 generate
7779
bus_request: process(host_req_i, acc_en)
7880
begin
79-
dev_req(i) <= host_req_i;
80-
dev_req(i).cyc <= host_req_i.cyc and acc_en(i);
81-
dev_req(i).stb <= host_req_i.stb and acc_en(i);
81+
dev_req(i) <= xbus_req_terminate_c; -- default: disabled
82+
if dev_en_list_c(i) then
83+
dev_req(i) <= host_req_i;
84+
dev_req(i).cyc <= host_req_i.cyc and acc_en(i);
85+
dev_req(i).stb <= host_req_i.stb and acc_en(i);
86+
end if;
8287
end process bus_request;
8388
end generate;
8489

@@ -90,7 +95,7 @@ begin
9095
tmp_v.ack := '0';
9196
tmp_v.err := '0';
9297
for i in 0 to num_devs_c-1 loop -- OR all enabled response buses
93-
if (acc_en(i) = '1') then
98+
if (acc_en(i) = '1') and dev_en_list_c(i) then
9499
tmp_v.data := tmp_v.data or dev_rsp(i).data;
95100
tmp_v.ack := tmp_v.ack or dev_rsp(i).ack;
96101
tmp_v.err := tmp_v.err or dev_rsp(i).err;

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