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Add rcc bus trait (#98)
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@burrbull @TheZoq2
burrbull authored and TheZoq2 committed Aug 17, 2019
1 parent cae0bec commit b1b1c87
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Showing 10 changed files with 172 additions and 98 deletions.
4 changes: 4 additions & 0 deletions CHANGELOG.md
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Expand Up @@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).

## [Unreleased]

### Added

- RCC `Bus` trait + private `Enable` and `Reset` traits

### Breaking changes

- Change timer/pwm init API
Expand Down
33 changes: 8 additions & 25 deletions src/adc.rs
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Expand Up @@ -4,7 +4,7 @@ use embedded_hal::adc::{Channel, OneShot};

use crate::gpio::Analog;
use crate::gpio::{gpioa, gpiob, gpioc};
use crate::rcc::{APB2, Clocks};
use crate::rcc::{APB2, Clocks, Enable, Reset};
use crate::dma::{Receive, TransferPayload, dma1::C1, CircBuffer, Transfer, W, RxDma};
use core::sync::atomic::{self, Ordering};
use cortex_m::asm::delay;
Expand Down Expand Up @@ -162,11 +162,7 @@ pub struct StoredConfig(AdcSampleTime, AdcAlign);

macro_rules! adc_hal {
($(
$ADC:ident: (
$init:ident,
$adcxen:ident,
$adcxrst:ident
),
$ADC:ident: ($init:ident),
)+) => {
$(

Expand Down Expand Up @@ -258,16 +254,15 @@ macro_rules! adc_hal {
}

fn reset(&mut self, apb2: &mut APB2) {
apb2.rstr().modify(|_, w| w.$adcxrst().set_bit());
apb2.rstr().modify(|_, w| w.$adcxrst().clear_bit());
$ADC::reset(apb2);
}

fn enable_clock(&mut self, apb2: &mut APB2) {
apb2.enr().modify(|_, w| w.$adcxen().set_bit());
$ADC::enable(apb2);
}

fn disable_clock(&mut self, apb2: &mut APB2) {
apb2.enr().modify(|_, w| w.$adcxen().clear_bit());
$ADC::disable(apb2);
}

fn calibrate(&mut self) {
Expand Down Expand Up @@ -500,27 +495,15 @@ impl Adc<ADC1> {
feature = "stm32f101",
))]
adc_hal! {
ADC1: (
adc1,
adc1en,
adc1rst
),
ADC1: (adc1),
}

#[cfg(any(
feature = "stm32f103",
))]
adc_hal! {
ADC1: (
adc1,
adc1en,
adc1rst
),
ADC2: (
adc2,
adc2en,
adc2rst
),
ADC1: (adc1),
ADC2: (adc2),
}

pub struct AdcPayload<PIN: Channel<ADC1>> {
Expand Down
7 changes: 3 additions & 4 deletions src/afio.rs
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@@ -1,7 +1,7 @@
//! # Alternate Function I/Os
use crate::pac::{afio, AFIO};

use crate::rcc::APB2;
use crate::rcc::{APB2, Enable, Reset};

use crate::gpio::{
Debugger,
Expand All @@ -17,9 +17,8 @@ pub trait AfioExt {

impl AfioExt for AFIO {
fn constrain(self, apb2: &mut APB2) -> Parts {
apb2.enr().modify(|_, w| w.afioen().set_bit());
apb2.rstr().modify(|_, w| w.afiorst().set_bit());
apb2.rstr().modify(|_, w| w.afiorst().clear_bit());
AFIO::enable(apb2);
AFIO::reset(apb2);

Parts {
evcr: EVCR { _0: () },
Expand Down
10 changes: 5 additions & 5 deletions src/dma.rs
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Expand Up @@ -111,7 +111,7 @@ pub struct R;
pub struct W;

macro_rules! dma {
($($DMAX:ident: ($dmaX:ident, $dmaXen:ident, $dmaXrst:ident, {
($($DMAX:ident: ($dmaX:ident, {
$($CX:ident: (
$chX:ident,
$htifX:ident,
Expand All @@ -129,7 +129,7 @@ macro_rules! dma {
use crate::pac::{$DMAX, dma1};

use crate::dma::{CircBuffer, DmaExt, Error, Event, Half, Transfer, W, RxDma, TxDma, TransferPayload};
use crate::rcc::AHB;
use crate::rcc::{AHB, Enable};

pub struct Channels((), $(pub $CX),+);

Expand Down Expand Up @@ -368,7 +368,7 @@ macro_rules! dma {
type Channels = Channels;

fn split(self, ahb: &mut AHB) -> Channels {
ahb.enr().modify(|_, w| w.$dmaXen().set_bit());
$DMAX::enable(ahb);

// reset the DMA control registers (stops all on-going transfers)
$(
Expand All @@ -384,7 +384,7 @@ macro_rules! dma {
}

dma! {
DMA1: (dma1, dma1en, dma1rst, {
DMA1: (dma1, {
C1: (
ch1,
htif1, tcif1,
Expand Down Expand Up @@ -422,7 +422,7 @@ dma! {
),
}),

DMA2: (dma2, dma2en, dma2rst, {
DMA2: (dma2, {
C1: (
ch1,
htif1, tcif1,
Expand Down
21 changes: 10 additions & 11 deletions src/gpio.rs
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Expand Up @@ -72,7 +72,7 @@ pub enum State {
}

macro_rules! gpio {
($GPIOX:ident, $gpiox:ident, $gpioy:ident, $iopxenr:ident, $iopxrst:ident, $PXx:ident, [
($GPIOX:ident, $gpiox:ident, $gpioy:ident, $PXx:ident, [
$($PXi:ident: ($pxi:ident, $i:expr, $MODE:ty, $CR:ident),)+
]) => {
/// GPIO
Expand All @@ -83,7 +83,7 @@ macro_rules! gpio {
use crate::hal::digital::v2::{InputPin, OutputPin, StatefulOutputPin, toggleable};
use crate::pac::{$gpioy, $GPIOX};

use crate::rcc::APB2;
use crate::rcc::{APB2, Enable, Reset};
use super::{
Alternate, Floating, GpioExt, Input,
OpenDrain,
Expand Down Expand Up @@ -112,10 +112,9 @@ macro_rules! gpio {
impl GpioExt for $GPIOX {
type Parts = Parts;

fn split(self, apb2: &mut APB2) -> Parts {
apb2.enr().modify(|_, w| w.$iopxenr().set_bit());
apb2.rstr().modify(|_, w| w.$iopxrst().set_bit());
apb2.rstr().modify(|_, w| w.$iopxrst().clear_bit());
fn split(self, apb: &mut APB2) -> Parts {
$GPIOX::enable(apb);
$GPIOX::reset(apb);

Parts {
crl: CRL { _0: () },
Expand Down Expand Up @@ -532,7 +531,7 @@ macro_rules! gpio {
}
}

gpio!(GPIOA, gpioa, gpioa, iopaen, ioparst, PAx, [
gpio!(GPIOA, gpioa, gpioa, PAx, [
PA0: (pa0, 0, Input<Floating>, CRL),
PA1: (pa1, 1, Input<Floating>, CRL),
PA2: (pa2, 2, Input<Floating>, CRL),
Expand All @@ -551,7 +550,7 @@ gpio!(GPIOA, gpioa, gpioa, iopaen, ioparst, PAx, [
PA15: (pa15, 15, Debugger, CRH),
]);

gpio!(GPIOB, gpiob, gpioa, iopben, iopbrst, PBx, [
gpio!(GPIOB, gpiob, gpioa, PBx, [
PB0: (pb0, 0, Input<Floating>, CRL),
PB1: (pb1, 1, Input<Floating>, CRL),
PB2: (pb2, 2, Input<Floating>, CRL),
Expand All @@ -570,7 +569,7 @@ gpio!(GPIOB, gpiob, gpioa, iopben, iopbrst, PBx, [
PB15: (pb15, 15, Input<Floating>, CRH),
]);

gpio!(GPIOC, gpioc, gpioa, iopcen, iopcrst, PCx, [
gpio!(GPIOC, gpioc, gpioa, PCx, [
PC0: (pc0, 0, Input<Floating>, CRL),
PC1: (pc1, 1, Input<Floating>, CRL),
PC2: (pc2, 2, Input<Floating>, CRL),
Expand All @@ -589,7 +588,7 @@ gpio!(GPIOC, gpioc, gpioa, iopcen, iopcrst, PCx, [
PC15: (pc15, 15, Input<Floating>, CRH),
]);

gpio!(GPIOD, gpiod, gpioa, iopden, iopdrst, PDx, [
gpio!(GPIOD, gpiod, gpioa, PDx, [
PD0: (pd0, 0, Input<Floating>, CRL),
PD1: (pd1, 1, Input<Floating>, CRL),
PD2: (pd2, 2, Input<Floating>, CRL),
Expand All @@ -608,7 +607,7 @@ gpio!(GPIOD, gpiod, gpioa, iopden, iopdrst, PDx, [
PD15: (pd15, 15, Input<Floating>, CRH),
]);

gpio!(GPIOE, gpioe, gpioa, iopeen, ioperst, PEx, [
gpio!(GPIOE, gpioe, gpioa, PEx, [
PE0: (pe0, 0, Input<Floating>, CRL),
PE1: (pe1, 1, Input<Floating>, CRL),
PE2: (pe2, 2, Input<Floating>, CRL),
Expand Down
13 changes: 6 additions & 7 deletions src/i2c.rs
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Expand Up @@ -6,7 +6,7 @@ use crate::gpio::{Alternate, OpenDrain};
use crate::hal::blocking::i2c::{Read, Write, WriteRead};
use nb::Error::{Other, WouldBlock};
use nb::{Error as NbError, Result as NbResult};
use crate::rcc::{Clocks, APB1};
use crate::rcc::{Clocks, APB1, Enable, Reset};
use crate::pac::{DWT, I2C1, I2C2};

/// I2C error
Expand Down Expand Up @@ -235,7 +235,7 @@ macro_rules! busy_wait_cycles {
}

macro_rules! hal {
($($I2CX:ident: ($i2cX:ident, $i2cXen:ident, $i2cXrst:ident),)+) => {
($($I2CX:ident: ($i2cX:ident),)+) => {
$(
impl<PINS> I2c<$I2CX, PINS> {
/// Configures the I2C peripheral to work in master mode
Expand All @@ -246,9 +246,8 @@ macro_rules! hal {
clocks: Clocks,
apb: &mut APB1,
) -> Self {
apb.enr().modify(|_, w| w.$i2cXen().set_bit());
apb.rstr().modify(|_, w| w.$i2cXrst().set_bit());
apb.rstr().modify(|_, w| w.$i2cXrst().clear_bit());
$I2CX::enable(apb);
$I2CX::reset(apb);

let pclk1 = clocks.pclk1().0;

Expand Down Expand Up @@ -476,6 +475,6 @@ macro_rules! hal {
}

hal! {
I2C1: (_i2c1, i2c1en, i2c1rst),
I2C2: (_i2c2, i2c2en, i2c2rst),
I2C1: (_i2c1),
I2C2: (_i2c2),
}
112 changes: 112 additions & 0 deletions src/rcc.rs
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Expand Up @@ -466,3 +466,115 @@ impl Clocks {
}
}

/// Bus associated to peripheral
pub trait RccBus {
/// Bus type;
type Bus;
}

/// Enable/disable peripheral
pub(crate) trait Enable: RccBus {
fn enable(apb: &mut Self::Bus);
fn disable(apb: &mut Self::Bus);
}

/// Reset peripheral
pub(crate) trait Reset: RccBus {
fn reset(apb: &mut Self::Bus);
}

macro_rules! bus {
($($PER:ident => ($apbX:ty, $peren:ident, $perrst:ident),)+) => {
$(
impl RccBus for crate::pac::$PER {
type Bus = $apbX;
}
impl Enable for crate::pac::$PER {
#[inline(always)]
fn enable(apb: &mut Self::Bus) {
apb.enr().modify(|_, w| w.$peren().set_bit());
}
#[inline(always)]
fn disable(apb: &mut Self::Bus) {
apb.enr().modify(|_, w| w.$peren().clear_bit());
}
}
impl Reset for crate::pac::$PER {
#[inline(always)]
fn reset(apb: &mut Self::Bus) {
apb.rstr().modify(|_, w| w.$perrst().set_bit());
apb.rstr().modify(|_, w| w.$perrst().clear_bit());
}
}
)+
}
}

macro_rules! ahb_bus {
($($PER:ident => ($peren:ident),)+) => {
$(
impl RccBus for crate::pac::$PER {
type Bus = AHB;
}
impl Enable for crate::pac::$PER {
#[inline(always)]
fn enable(apb: &mut Self::Bus) {
apb.enr().modify(|_, w| w.$peren().set_bit());
}
#[inline(always)]
fn disable(apb: &mut Self::Bus) {
apb.enr().modify(|_, w| w.$peren().clear_bit());
}
}
)+
}
}

#[cfg(any(
feature = "stm32f100",
feature = "stm32f103",
))]
bus! {
TIM1 => (APB2, tim1en, tim1rst),
}
#[cfg(feature = "stm32f103")]
bus! {
ADC2 => (APB2, adc2en, adc2rst),
CAN1 => (APB1, canen, canrst),
}
bus! {
ADC1 => (APB2, adc1en, adc1rst),
AFIO => (APB2, afioen, afiorst),
GPIOA => (APB2, iopaen, ioparst),
GPIOB => (APB2, iopben, iopbrst),
GPIOC => (APB2, iopcen, iopcrst),
GPIOD => (APB2, iopden, iopdrst),
GPIOE => (APB2, iopeen, ioperst),
I2C1 => (APB1, i2c1en, i2c1rst),
I2C2 => (APB1, i2c2en, i2c2rst),
SPI1 => (APB2, spi1en, spi1rst),
SPI2 => (APB1, spi2en, spi2rst),
TIM2 => (APB1, tim2en, tim2rst),
TIM3 => (APB1, tim3en, tim3rst),
TIM4 => (APB1, tim4en, tim4rst),
USART1 => (APB2, usart1en, usart1rst),
USART2 => (APB1, usart2en, usart2rst),
USART3 => (APB1, usart3en, usart3rst),
WWDG => (APB1, wwdgen, wwdgrst),
}
#[cfg(feature = "high")]
bus! {
TIM6 => (APB1, tim6en, tim6rst),
TIM7 => (APB1, tim7en, tim7rst),
}

ahb_bus! {
CRC => (crcen),
DMA1 => (dma1en),
DMA2 => (dma2en),
}

#[cfg(feature = "high")]
ahb_bus! {
FSMC => (fsmcen),
}
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