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Added DMA configurable timeout register #1246

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Merged
merged 9 commits into from
Mar 31, 2025
Merged

Added DMA configurable timeout register #1246

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c51c2ea
added configurable timeout
mmishra9 Mar 18, 2025
8d3810b
fixed ret type
mmishra9 Mar 18, 2025
f6a9d9d
fixed ret type
mmishra9 Mar 18, 2025
4aede17
Updated record name
mmishra9 Mar 24, 2025
af75e16
fixed typos
mmishra9 Mar 24, 2025
8da42aa
updated retType
mmishra9 Mar 25, 2025
af7a678
updated retType
mmishra9 Mar 25, 2025
1b85b9c
bug fix
mmishra9 Mar 25, 2025
0a81375
updated mapping
mmishra9 Mar 26, 2025
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4 changes: 3 additions & 1 deletion axi/dma/rtl/AxiDmaPkg.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -194,6 +194,7 @@ package AxiDmaPkg is
maxSize : slv(31 downto 0);
contEn : sl;
buffId : slv(31 downto 0);
timout : slv(31 downto 0);
end record;

constant AXI_WRITE_DMA_DESC_ACK_INIT_C : AxiWriteDmaDescAckType := (
Expand All @@ -204,7 +205,8 @@ package AxiDmaPkg is
dropEn => '0',
maxSize => (others=>'0'),
contEn => '0',
buffId => (others=>'0')
buffId => (others=>'0'),
timout => x"0000FFFF"
);

type AxiWriteDmaDescAckArray is array (natural range<>) of AxiWriteDmaDescAckType;
Expand Down
7 changes: 6 additions & 1 deletion axi/dma/rtl/v2/AxiStreamDmaV2Desc.vhd
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Expand Up @@ -145,6 +145,7 @@ architecture rtl of AxiStreamDmaV2Desc is
buffWrCache : slv(3 downto 0);
enableCnt : slv(7 downto 0);
idBuffThold : Slv32Array(7 downto 0);
wrTimout : slv(31 downto 0);

-- FIFOs
fifoDin : slv(31 downto 0);
Expand Down Expand Up @@ -222,6 +223,7 @@ architecture rtl of AxiStreamDmaV2Desc is
buffWrCache => (others => '0'),
enableCnt => (others => '0'),
idBuffThold => (others => (others => '0')),
wrTimout => x"0000FFFF",
-- FIFOs
fifoDin => (others => '0'),
wrFifoWr => (others => '0'),
Expand Down Expand Up @@ -433,7 +435,7 @@ begin
axiSlaveRegister(regCon, x"000", 0, v.enable);
axiSlaveRegisterR(regCon, x"000", 8, r.enableCnt); -- Count the number of times enable transitions from 0->1
axiSlaveRegisterR(regCon, x"000", 16, '1'); -- Legacy DESC_128_EN_C constant (always 0x1 now)
axiSlaveRegisterR(regCon, x"000", 24, toSlv(4, 8)); -- Version Number for aes-stream-driver to case on
axiSlaveRegisterR(regCon, x"000", 24, toSlv(5, 8)); -- Version Number for aes-stream-driver to case on
axiSlaveRegister(regCon, x"004", 0, v.intEnable);
axiSlaveRegister(regCon, x"008", 0, v.contEn);
axiSlaveRegister(regCon, x"00C", 0, v.dropEn);
Expand Down Expand Up @@ -486,6 +488,8 @@ begin

axiSlaveRegister(regCon, x"084", 0, v.intHoldoff);

axiSlaveRegister(regCon, x"088", 0, v.wrTimout);

for i in 0 to 7 loop
axiSlaveRegister(regCon, toSlv(144 + i*4, 12), 0, v.idBuffThold(i)); -- 0x090 - 0xAC
axiSlaveRegisterR(regCon, toSlv(176 + i*4, 12), 0, r.idBuffCount(i)); -- 0x0B0 - 0xCC
Expand Down Expand Up @@ -583,6 +587,7 @@ begin
v.dmaWrDescAck(i).dropEn := r.dropEn;
v.dmaWrDescAck(i).contEn := r.contEn;
v.dmaWrDescAck(i).maxSize := r.maxSize;
v.dmaWrDescAck(i).timeout := r.wrTimout;

v.dmaWrDescAck(i).buffId(27 downto 0) := wrFifoDout(27 downto 0);

Expand Down
5 changes: 3 additions & 2 deletions axi/dma/rtl/v2/AxiStreamDmaV2Write.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -81,7 +81,7 @@ architecture rtl of AxiStreamDmaV2Write is
result : slv(1 downto 0);
reqCount : slv(31 downto 0);
ackCount : slv(31 downto 0);
stCount : slv(15 downto 0);
stCount : slv(31 downto 0);
awlen : slv(AXI_CONFIG_G.LEN_BITS_C-1 downto 0);
axiLen : AxiLenType;
wMaster : AxiWriteMasterType;
Expand Down Expand Up @@ -271,6 +271,7 @@ begin
v.dmaWrTrack.metaAddr := dmaWrDescAck.metaAddr;
v.dmaWrTrack.address := dmaWrDescAck.address;
v.dmaWrTrack.maxSize := dmaWrDescAck.maxSize;
v.dmaWrTrack.timout := dmaWrDescAck.timout;

-- Descriptor return calls for dumping frame?
if dmaWrDescAck.dropEn = '1' then
Expand Down Expand Up @@ -473,7 +474,7 @@ begin
v.dmaWrDescRet.valid := '1';
v.state := IDLE_S;
-- Check for ACK timeout
elsif (r.stCount = x"FFFF") then
elsif (r.stCount = r.dmaWrTrack.timout) then
-- Set the flags
v.dmaWrDescRet.result(1 downto 0) := "11";
v.dmaWrDescRet.valid := '1';
Expand Down