Add a lot of files for zybo board, so that we can use command line to…

.gitmodules

@@ -6,4 +6,4 @@
 	url = https://github.com/sifive/sifive-blocks.git
 [submodule "fpga-shells"]
 	path = fpga-shells
-	url = https://github.com/sifive/fpga-shells
+	url = https://github.com/gongqingfeng/fpga-shells.git

Makefile.e300zybodevkit

@@ -0,0 +1,22 @@
+# See LICENSE for license details.
+base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
+BUILD_DIR := $(base_dir)/builds/e300zybodevkit
+FPGA_DIR := $(base_dir)/fpga-shells/xilinx
+MODEL := E300ZyboDevKitFPGAChip
+PROJECT := sifive.freedom.everywhere.e300zybodevkit
+CONFIG_PROJECT := sifive.freedom.everywhere.e300zybodevkit
+export CONFIG := E300ZyboDevKitConfig
+export BOARD := zybo
+export BOOTROM_DIR := $(base_dir)/bootrom/xip
+
+rocketchip_dir := $(base_dir)/rocket-chip
+sifiveblocks_dir := $(base_dir)/sifive-blocks
+VSRCS := \
+	$(rocketchip_dir)/vsrc/AsyncResetReg.v \
+	$(rocketchip_dir)/vsrc/plusarg_reader.v \
+	$(sifiveblocks_dir)/vsrc/SRLatch.v \
+	$(FPGA_DIR)/common/vsrc/PowerOnResetFPGAOnly.v \
+	$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v \
+	$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).v
+
+include common.mk

README.md

@@ -1,95 +1,110 @@
-Freedom
-=======
+# Freedom Repository
 
 This repository contains the RTL created by SiFive for its Freedom E300 and U500
-platforms. The Freedom E310 Arty FPGA Dev Kit implements the Freedom E300
-Platform and is designed to be mapped onto an [Arty FPGA Evaluation
-Kit](https://www.xilinx.com/products/boards-and-kits/arty.html). The Freedom
-U500 VC707 FPGA Dev Kit implements the Freedom U500 Platform and is designed to
-be mapped onto a [VC707 FPGA Evaluation
-Kit](https://www.xilinx.com/products/boards-and-kits/ek-v7-vc707-g.html).
-Both systems boot autonomously and can be controlled via an external debugger.
+platforms. The Zybo Dev Kit 
+implement the Freedom E300 Platform.
+
+Note: The branch [freedom_zybo](https://github.com/gongqingfeng/freedom/tree/freedom_zybo)  is for Zybo Dev Kit. If you use Ebaz4205 FPGA Board, please switch to the branch [ebaz4205](https://github.com/gongqingfeng/freedom/tree/ebaz4205).
+
 
 Please read the section corresponding to the kit you are interested in for
 instructions on how to use this repo.
 
-Software Requirement
+## Software Requirement
 --------------------
-
-To compile the bootloaders for both Freedom E300 Arty and U500 VC707
-FPGA dev kits, the RISC-V software toolchain must be installed locally and
+To compile the bootloaders for Freedom E300 Zybo, the RISC-V software toolchain must be installed locally and
 set the $(RISCV) environment variable to point to the location of where the
-RISC-V toolchains are installed. You can build the toolchain from scratch
-or download the tools here: https://www.sifive.com/products/tools/
-
-
-Freedom E300 Arty FPGA Dev Kit
-------------------------------
-
-The Freedom E300 Arty FPGA Dev Kit implements a Freedom E300 chip.
-
-### How to build
-
-The Makefile corresponding to the Freedom E300 Arty FPGA Dev Kit is
-`Makefile.e300artydevkit` and it consists of two main targets:
-
-- `verilog`: to compile the Chisel source files and generate the Verilog files.
-- `mcs`: to create a Configuration Memory File (.mcs) that can be programmed
-onto an Arty FPGA board.
-
-To execute these targets, you can run the following commands:
+RISC-V toolchains are installed. You must pay attention to the version, or 
+you may meet much trouble.
 
+First, you should download the repository(it may take much time. Maybe vpn need?):
 ```sh
-$ make -f Makefile.e300artydevkit verilog
-$ make -f Makefile.e300artydevkit mcs
+$ git clone --recursive https://github.com/gongqingfeng/freedom.git
+# you can also use gitee
+$ git clone --recursive https://gitee.com/gongqingfeng/freedom.git
 ```
 
-Note: This flow requires vivado 2017.1. Old versions are known to fail.
-
-These will place the files under `builds/e300artydevkit/obj`.
+Second, you should enter the work dir like this:
+```sh
+$ cd freedom
+# check your branch
+git branch
+# if your branch is not freedom_zybo, you should switch to the branch freedom_zybo
+git checkout freedom_zybo
+```
 
-Note that in order to run the `mcs` target, you need to have the `vivado`
-executable on your `PATH`.
+Optionally, if you did not compile the toolchain and you do like this(it will take much time):
+```sh
+$ cd rocket-chip/riscv-tools
+$ export RISCV=/yout/install/toolchain/location # eg: export RISCV=/home/xx/xxx/risc-v_dev/tools
+$ export MAKEFLAGS="$MAKEFLAGS -jN" # Assuming you have N cores on your host system
+$ ./build.sh
+```
+Ubuntu packages needed:
+```sh
+$ sudo apt-get install autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev libusb-1.0-0-dev gawk build-essentia
+```
+OK! Let's go ahead!
 
-### Bootrom
+## Freedom E300 Zybo dev Kit
 
-The default bootrom consists of a program that immediately jumps to address
-0x20400000, which is 0x00400000 bytes into the SPI flash memory on the Arty
-board.
+The Freedom E300 Dev Kit implements a Freedom E300 chip.
 
-### Using the generated MCS Image
+### How to build
+Noets: I use Ubuntu16.04
 
-For instructions for getting the generated image onto an FPGA and programming it with software using the [Freedom E SDK](https://github.com/sifive/freedom-e-sdk), please see the [Freedom E310 Arty FPGA Dev Kit Getting Started Guide](https://www.sifive.com/documentation/freedom-soc/freedom-e300-arty-fpga-dev-kit-getting-started-guide/).
+Install java:
+```sh
+$ sudo apt install openjdk-8-jdk
+```
 
-Freedom U500 VC707 FPGA Dev Kit
--------------------------------
+Install sbt:
+```sh
+$ echo "deb https://repo.scala-sbt.org/scalasbt/debian all main" | sudo tee /etc/apt/sources.list.d/sbt.list
+$ echo "deb https://repo.scala-sbt.org/scalasbt/debian /" | sudo tee /etc/apt/sources.list.d/sbt_old.list
+$ curl -sL "https://keyserver.ubuntu.com/pks/lookup?op=get&search=0x2EE0EA64E40A89B84B2DF73499E82A75642AC823" | sudo apt-key add
+$ sudo apt-get update
+$ sudo apt-get install sbt
+```
 
-The Freedom U500 VC707 FPGA Dev Kit implements the Freedom U500 platform.
+if you occur problem like this:
+```sh
+error: error while loading package, Missing dependency 'object java.lang.Object in compiler mirror', required by
+```
+you should switch java version to 8:
+```sh
+$ sudo update-alternatives --config java
+$ sudo update-alternatives --config javac
+```
 
-### How to build
+If you are not in freedom directory, please enter the dir like this:
+```sh
+$ cd freedom
+```
 
-The Makefile corresponding to the Freedom U500 VC707 FPGA Dev Kit is
-`Makefile.u500vc707devkit` and it consists of two main targets:
+The Makefile corresponding to the Freedom E300 Zybo Dev Kit is
+`Makefile.e300zybodevkit` and it consists of several targets:
 
 - `verilog`: to compile the Chisel source files and generate the Verilog files.
-- `mcs`: to create a Configuration Memory File (.mcs) that can be programmed
-onto an VC707 FPGA board.
+- `project`: to compile the Chisel source files and generate the vivado project.
+- `vivado`: to launch the vivado project with GUI mode. So you can systhesis, implement and generate bitstream by yourself.
 
 To execute these targets, you can run the following commands:
 
 ```sh
-$ make -f Makefile.u500vc707devkit verilog
-$ make -f Makefile.u500vc707devkit mcs
+$ make -f Makefile.e300zybodevkit verilog
+$ make -f Makefile.e300zybodevkit project
+$ make -f Makefile.e300zybodevkit vivado
 ```
+Note1: This lab tested within vivado 2016.2.
 
-Note: This flow requires vivado 2016.1. Newer versions are known to fail.
+Note2: Before you generate bitstream, you are supposed to add the `freedom/fpga-shells/xilinx/zybo/tcl/no_connect.tcl` file to your Bitstream Settings's tcl.pre blank line. Otherwise, you will get errors.
 
-These will place the files under `builds/u500vc707devkit/obj`.
+The vivado project files place under `builds/e300zybodevkit` and the *.v files place under `builds/e300zybodevkit/obj`.
 
-Note that in order to run the `mcs` target, you need to have the `vivado`
+Note that in order to run the `projest` and `vivado`target, you need to have the `vivado`
 executable on your `PATH`.
 
 ### Bootrom
 
-The default bootrom consists of a bootloader that loads a program off the SD
-card slot on the VC707 board.
+The default bootrom consists of a program that can blink three LED from address 0x0001FFFF on the Zybo Dev Kit.

bootrom/xip/xip.S

@@ -8,8 +8,51 @@
 _start:
   csrr a0, mhartid
   la a1, dtb
-  li t0, XIP_TARGET_ADDR
-  jr t0
+1:
+  li x1, 0x7
+  li x2,0x10012008   // make GPIO0  GPIO1  GPIO2 out port
+  sw x1,0(x2)
+
+
+  li x3, 0
+  li x5,1 
+
+2:
+
+// light Green LED2,  then wait few seconds
+  li x1, 0x04
+  li x2,0x1001200C
+  sw x1,0(x2)
+
+
+  li x4,0x1dfd240
+3:
+  sub x4,x4,x5
+  bne x4,x3,3b
+
+// light Green LED1,  then wait few seconds
+  li x1, 0x02
+  li x2,0x1001200C
+  sw x1,0(x2)
+
+
+  li x4,0x1dfd240
+4:
+  sub x4,x4,x5
+  bne x4,x3,4b
+
+// light Green LED0,  then wait few seconds
+  li x1, 0x01
+  li x2,0x1001200C
+  sw x1,0(x2)
+
+  li x4,0x1dfd240
+5:
+  sub x4,x4,x5
+  bne x4,x3,5b
+
+  j 2b
+  nop
 
   .section .rodata
 dtb:

common.mk

@@ -26,6 +26,8 @@ EXTRA_FPGA_VSRCS ?=
 PATCHVERILOG ?= ""
 BOOTROM_DIR ?= ""
 
+proj_name = $(BOARD)_freedom_$(CONFIG)
+
 base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
 export rocketchip_dir := $(base_dir)/rocket-chip
 SBT ?= java -jar $(rocketchip_dir)/sbt-launch.jar
@@ -76,6 +78,23 @@ f := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).vsrcs.F
 $(f):
 	echo $(VSRCS) > $@
 
+# Build .xpr
+project := $(BUILD_DIR)/$(proj_name)/$(proj_name).xpr
+$(project): $(romgen) $(f)
+	cd $(BUILD_DIR); vivado \
+		-nojournal -mode batch \
+		-source $(fpga_common_script_dir)/project.tcl \
+		-tclargs \
+		-top-module "$(MODEL)" \
+		-F "$(f)" \
+		-ip-vivado-tcls "$(shell find '$(BUILD_DIR)' -name '*.project.tcl')" \
+		-board "$(BOARD)" \
+		-config "$(CONFIG)" 
+project: $(project)
+
+vivado: $(project)
+	vivado -nojournal -nolog $(project) 
+
 bit := $(BUILD_DIR)/obj/$(MODEL).bit
 $(bit): $(romgen) $(f)
 	cd $(BUILD_DIR); vivado \

src/main/scala/everywhere/e300zybodevkit/Config.scala

@@ -0,0 +1,65 @@
+// See LICENSE for license details.
+package sifive.freedom.everywhere.e300zybodevkit
+
+import freechips.rocketchip.config._
+import freechips.rocketchip.coreplex._
+import freechips.rocketchip.devices.debug._
+import freechips.rocketchip.devices.tilelink._
+import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase}
+import freechips.rocketchip.system._
+import freechips.rocketchip.tile._
+
+import sifive.blocks.devices.mockaon._
+import sifive.blocks.devices.gpio._
+import sifive.blocks.devices.pwm._
+import sifive.blocks.devices.spi._
+import sifive.blocks.devices.uart._
+import sifive.blocks.devices.i2c._
+
+// Default FreedomEConfig
+class DefaultFreedomEConfig extends Config (
+  new WithNBreakpoints(2)        ++
+  new WithNExtTopInterrupts(0)   ++
+  new WithJtagDTM                ++
+  new TinyConfig
+)
+
+// Freedom E300 Zybo Dev Kit Peripherals
+class E300DevKitPeripherals extends Config((site, here, up) => {
+  case PeripheryGPIOKey => List(
+    GPIOParams(address = 0x10012000, width = 32, includeIOF = true))
+  case PeripheryPWMKey => List(
+    PWMParams(address = 0x10015000, cmpWidth = 8),
+    PWMParams(address = 0x10025000, cmpWidth = 16),
+    PWMParams(address = 0x10035000, cmpWidth = 16))
+  case PeripherySPIKey => List(
+    SPIParams(csWidth = 4, rAddress = 0x10024000, sampleDelay = 3),
+    SPIParams(csWidth = 1, rAddress = 0x10034000, sampleDelay = 3))
+  case PeripherySPIFlashKey => List(
+    SPIFlashParams(
+      fAddress = 0x20000000,
+      rAddress = 0x10014000,
+      sampleDelay = 3))
+  case PeripheryUARTKey => List(
+    UARTParams(address = 0x10013000),
+    UARTParams(address = 0x10023000))
+  case PeripheryI2CKey => List(
+    I2CParams(address = 0x10016000))
+  case PeripheryMockAONKey =>
+    MockAONParams(address = 0x10000000)
+  case PeripheryMaskROMKey => List(
+    MaskROMParams(address = 0x10000, name = "BootROM"))
+})
+
+// Freedom E300 Zybo Dev Kit Peripherals
+class E300ZyboDevKitConfig extends Config(
+  new E300DevKitPeripherals    ++
+  new DefaultFreedomEConfig().alter((site,here,up) => {
+    case DTSTimebase => BigInt(32768)
+    case JtagDTMKey => new JtagDTMConfig (
+      idcodeVersion = 2,
+      idcodePartNum = 0x000,
+      idcodeManufId = 0x489,
+      debugIdleCycles = 5)
+  })
+)