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This repository has been archived by the owner on Mar 2, 2021. It is now read-only.

Issues: sifive/freedom

64 Open 73 Closed
64 Open 73 Closed
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Issues list

Port to my fpga board
#173 opened Mar 1, 2021 by quantrpeter
This project is incompatible with the latest Arty A7 35T
#171 opened Feb 19, 2021 by lindemer
4
Verilator: mistake in installation instructions
#170 opened Feb 19, 2021 by AntonHermann
Accessing Arty-35T DRAM
#169 opened Feb 16, 2021 by denishoornaert
1
How to Simulate e300artydevkit?
#168 opened Jan 6, 2021 by kvtam
Where is Class “DevKitU500FPGADesign_WithDevKit100MHz”？
#167 opened Dec 15, 2020 by liyewen521
2
Spratan 6 porting issue
#166 opened Oct 25, 2020 by mopplayer
System hangs after AXI4-Lite register read
#165 opened Oct 14, 2020 by manox
Fedora on VC707 Board
#164 opened Oct 11, 2020 by jakesanggulee
sample code to test modes
#162 opened Aug 31, 2020 by pankajjoshi347
1
clk sync JTAG and Debug module
#161 opened Aug 24, 2020 by ohadbox
How to replace old kernel with new
#160 opened Jul 27, 2020 by pankajjoshi347
problems when clone the pixman
#159 opened Jul 22, 2020 by Daniel-bboy
how to add MMIO peripherals to U500 design
#158 opened Jun 16, 2020 by shirlynan
1
Booting Linux file system from SD and enable partition VC707-U500
#157 opened Jun 8, 2020 by jalezeta
L2 inclusive cache latency
#156 opened Jun 8, 2020 by gdessouky
Use Boom core in Freedom
#153 opened May 19, 2020 by manox
3
QSFP-Ethernet on VCU118
#152 opened May 8, 2020 by manox
3
Updated master?
#151 opened Apr 26, 2020 by jctullos
35
how to modify DefaultFreedomEConfig?
#150 opened Apr 11, 2020 by zhangliang1997
1
SD Card is showing strange behavior
#149 opened Feb 13, 2020 by Iripi97
2
submodule verification
#148 opened Jan 4, 2020 by minisparrow
Using VC709 instead of VC707
#147 opened Nov 24, 2019 by abdelrahmanhussein
3
How to add Inclusive cache to Freedom?
#144 opened Nov 6, 2019 by yintianyu
1
How to insert a delay module between the CPU and memory controller?
#138 opened Oct 13, 2019 by wwMark
2
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