Repository navigation
[Feat] KVShard: Integrate GLM DSA/MTP with PD and CPU HiCache - #42973
Merged
Merged
Conversation
This was referenced Oct 7, 2026
HZY-Wade
force-pushed
the
codex/kvshard-dsa-hicache
branch
from
October 8, 2026 04:00
e02f445 to
937892a
Compare
HZY-Wade
marked this pull request as ready for review
October 13, 2026 03:50
HZY-Wade
requested review from
1am9trash,
ByronHsu,
Fridge003,
HaiShaw,
Qiaolin-Yu,
YAMY1234,
Ying1123,
alphabetc1,
hanming-lu,
hebiao064,
hnyls2002,
huangtingwei9988,
hubertlu-tw,
hzh0425,
ispobock,
kkHuang-amd,
merrymercy,
rainj-me,
xiezhq-hermann and
yizhang2077
as code owners
October 13, 2026 03:50
HZY-Wade
requested review from
JustinTong0323,
wisclmy0611 and
zijiexia
as code owners
October 26, 2026 14:55
Contributor
Preview approval requiredThis pull request comes from a fork, so Mintlify won't build a preview until someone with write access approves commit |
Contributor
Author
|
/rerun-failed-ci |
hzh0425
reviewed
Oct 26, 2026
| --enable-metrics --enable-cache-report | ||
| ) | ||
|
|
||
| python3 -m sglang.launch_server "${COMMON_ARGS[@]}" \ |
Collaborator
There was a problem hiding this comment.
should optimize this command's style, like:
DeepSeek Multi-Node
# prefill 0
python -m sglang.launch_server \
--model-path deepseek-ai/DeepSeek-V3-0324 \
--disaggregation-ib-device ${device_name} \
--disaggregation-mode prefill \
--host ${local_ip} \
--port 30000 \
--trust-remote-code \
--dist-init-addr ${prefill_master_ip}:5000 \
--nnodes 2 \
--node-rank 0 \
--tp-size 16 \
--attn-dp-size 8 \
--moe-a2a-backend deepep \
--mem-fraction-static 0.8
# prefill 1
python -m sglang.launch_server \
--model-path deepseek-ai/DeepSeek-V3-0324 \
--disaggregation-ib-device ${device_name} \
--disaggregation-mode prefill \
--host ${local_ip} \
--port 30000 \
--trust-remote-code \
--dist-init-addr ${prefill_master_ip}:5000 \
--nnodes 2 \
--node-rank 1 \
--tp-size 16 \
--attn-dp-size 8 \
--moe-a2a-backend deepep \
--mem-fraction-static 0.8
Contributor
Author
|
/rerun-failed-ci |
1 similar comment
Contributor
Author
|
/rerun-failed-ci |
Contributor
Author
|
Additional GLM-5.3 accuracy evaluation results from my run, using the
|
Collaborator
|
/rerun-test test/registered/unit/disaggregation/test_dsa_sharded_pd_transfer.py |
Collaborator
Contributor
|
🚀 |
Collaborator
|
/rerun-test -c |
Contributor
|
🚀 🚀 |
Collaborator
|
thanks @HZY-Wade |
3 of 4 tasks
jambow0320
added a commit
to jambow0320/sglang
that referenced
this pull request
Oct 27, 2026
The test from sgl-project#42973 replaced _transfer_data, which the Mooncake transport extraction removed. Attach a real MooncakeTransport over a memory-copy engine instead; the byte-level checks are unchanged.
This was referenced Oct 27, 2026
5 tasks done
Venkat2811
added a commit
to datacrunch-research/sglang
that referenced
this pull request
Oct 30, 2026
…attach check sgl-project#42973 made StorageAttachment ask page_interleave_shard_size() about cache.token_to_kv_pool_allocator before attaching a storage backend. The role-local DCP attach tests (ported with sgl-project#41695) build their cache as a SimpleNamespace without that attribute, so 14 of them stopped at an AttributeError. Give the fake a plain namespace there: a stock allocator, shard size 1, which is what those tests mean. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
detain
added a commit
to detain/sglang
that referenced
this pull request
Oct 30, 2026
…nchors -- entries 244/247-era surfaces, 301, sgl-project#44842, sgl-project#42973 Battery damage classes re-derived per-file POST-MERGE (CVD=9, prod venv, PYTHONPATH=python) with the B5-3/B5-4 code state: (1) test_modelopt_nvfp4_moe_scales 2F (SUBFAILED pair): merge took upstream's sgl-project#45289 test file and DROPPED the fork's entry-244 stub block (the small-M workspace gate reads placement attrs in process_weights_after_loading regardless of kernel support -- kwargs evaluate first). Stub block re-planted VERBATIM from the 309 tip. 20P/44sub (>= the pre-merge 20P/42sub: upstream grew two subtests). (2) test_fp4_gemm_backend_sm120 3F: upstream sgl-project#44842 (in-range) grew the autotune gate with get_parallel().enable_kv_cache_sharding (sgl-project#42973) + the FP8->MXFP8 module-tree pre-check; the gate tests' stubs predate both. Test re-anchored (get_parallel stub + empty module tree); the three beliefs (b12x keeps the pass, cutlass autotunes, marlin doesn't) unchanged. 12P/0F. (3) test_mem_pool_ep_unit 1F: the DOCUMENTED tip-era class, now attributed exactly: the test's id-contract predates entry-247 -- dispatcher skip TRUE for b12x vs the stale expected-False. Set re-pinned: dispatcher_global_ids += FLASHINFER_B12X_W4A16 (its expert_map contract, the very arm B5-3 re-planted into _keeps_global_expert_ids) and the LoRA subtraction gains b12x (no LoRA path). EXPERIMENTAL_SGL_TRTLLM verified HARMLESS without its removed arm: is_flashinfer_trtllm() covers the value by design (utils.py:212-217), confirming B5-3's upstream-churn verdict on that branch. 49P/0F/4sub -- class CLOSED, one fewer env-class than the pre-merge baseline. ENV CLASSES CONFIRMED (not new, not fixable here): trtllm_gen 8F == documented 8F; moe_fused_gate 52F == documented ~52F ALL 'No CUDA GPUs are available'; triton_fused_moe 96F == documented ~96F; round_robin 38F (documented 37 + 1 upstream-grown CUDA case, ALL 'No CUDA GPUs'); mega_moe_deepgemm 1F == documented 1F (test's deep_gemm fake vs mxfp4.py's in-range wrapper import -- NOT my redirect: fails identically at b3207c7 with mega_moe pre-B5-3; B2 marker :905 covers the test-side fix). GATE RE-CHECK: standard_dispatcher 21P (grew again, green), runner_backend 16P, fold probe 9P, overrides 121P/1S/210sub.
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.

Motivation
Co-author: @Shunkangz
Connect GLM DSA/MTP serving to page-sharded KV caches so prefill, P/D transfer and CPU HiCache preserve the same ownership for target/draft latent KV and DSA indexer keys/scales.
Dependencies and review scope
Base: upstream main
5987ec82ed. Current head:346068aaa329cf1692fbb6031f60469fdac77dcb.DSA attention/indexer support (#44280), MTP pool/scratch support (#40929), and the control-plane/pool/basic-PD prerequisites are already merged.
The remaining unmerged prerequisite is #43778, pinned at
6d1e510b2429a36fe499943ff075472d995d8457. Its three implementation commits are rebased onto this main base with Shunkang's author attribution preserved. The dependency snapshot is152e93348ad825449c484fbee2068fc614116c67.Review the integration increment: HZY-Wade/sglang@codex/kvshard-glm-dependencies-20261026-clean...codex/kvshard-dsa-hicache
GitHub's main-based Files changed view also includes #43778. Rust support is separate in #46445; this PR contains no Rust implementation and selects Python for sharded launches when the tree backend is unset.
Modifications
start_ownerto backups only when the tree node has a shard owner. Preserve owner zero and the non-sharded controller's existing call signature.CustomTestCaseconvention.Supported configuration: CUDA PD-prefill, interleave CP > 1, PP1, TRTLLM DSA prefill/decode, FP8 E4M3/page64, Mooncake, and uncompressed index_kpool=1. Optional MTP is single-layer GLM NextN EAGLE with topk=1. CPU HiCache uses cache mode, kernel I/O and layer_first/page_first. L3, external linkers, DSA layer splitting, HiSparse and two-batch overlap are outside this combination. Decode remains unsharded.
Configuration requirements, paired launch example and validation guidance
Accuracy Tests
f01f901a6a(runtime source unchanged by the following documentation/fixture commits): 200 tests and 140 subtests passed, 2 skipped, 1 deselected. This covers owner-aware PD transfer, allocator/rotation invariants, scratch sizing, scheduler admission, host-transfer dispatch, launch compatibility and controller event ordering.unexpected keyword argument 'start_owner'failure and passes with8620dbdaa1.git diff --checkpass. Mintlify 4.2.559 reports no broken links with anchor/redirect checks. Both documented launch commands pass the CLI parser and their shell block passesbash -n.Hardware E2E status
Passed on current head
346068aaa329cf1692fbb6031f60469fdac77dcb, Base attempt 2.test_dsa_glm52_pd_kv_shard_hicache.pyactually ran and passed, with a 273-second suite duration. The test method completed withRan 1 test ... OK; this was not a collection-only or skipped result.test_decode_hicache_l2.py(36 seconds), which previously exposed the non-sharded backup signature regression.MC_FORCE_MNNVL=trueandSGLANG_MOONCAKE_CUSTOM_MEM_POOL=NVLINK. The NVLink allocator supplies exportable KV buffers; the runner's wheel does not providenvlink_intra.The launch example has separate prefill/decode commands with one option per line, addressing review comment 4379290548. CLI arguments are unchanged; both examples match the E2E transport settings. Shell syntax, CLI parsing, allocator selection equivalence, pre-commit and Mintlify anchor/link checks pass.
The separate existing GLM-5.2 layer-split accuracy rerun passed at 0.9422632794457275, above the unchanged 0.935 GSM8K threshold; the full job passed 2/2 test files. The previous attempt scored 0.9345650500384911. Both attempts tested merge
e79b8b8c52735038eb60edcacff7a3e6f24ea69ewith KV sharding disabled, and no code or threshold changes were made between them. The successful rerun does not establish the cause of the score variation.On current head, Base attempt 3 and Extra attempt 3 are both successful. Arm64 and Xeon retain separately investigated failures in unchanged CPU-operator/parser paths; the complete platform matrix is not all green.
Speed Tests and Profiling
A controlled production replay is still pending; no throughput or latency speedup is claimed.
For the requested comparison, use the same model revision, hardware, runtime, P/D topology, memory budget, request order, concurrency and warm-up policy. Report device/host hit tokens, TTFT percentiles, throughput, peak memory and answer correctness for replicated/deduplicated KV and KV sharding. CPU unit-test counts and increased logical capacity are not performance measurements.
Checklist
CI States
Latest PR Test (Base): ✅ Run #40354128180
Latest PR Test (Extra): ✅ Run #40354126514
Latest PR Test (AMD ROCm 10): ⏳ Run #40354127190