[AMD][ROCm] Add optional device-resident ordering-edge runtime build (rocm-systems#11212)

[karverma-amd]

Motivation

On ROCm, cross-stream / hipgraph dependency polls default to host-visible memory and cross PCIe. With GPU_MAX_HW_QUEUES > 4 this manifests as a low-concurrency decode regression. ROCm/rocm-systems#11212 adds device-resident ordering edges (hsa_amd_signal_create_v2 + HSA_AMD_SIGNAL_CREATE_DEVICE_MEM_VALUE_WORD in ROCr, plus the CLR side that names a device-resident ordering-edge value word on cross-queue barrier deps) so those polls come from device-local VRAM instead. vLLM adopted the same mitigation in vllm-project/vllm#55099.

What this PR adds

An optional, opt-in docker/rocm-ordering-edge.Dockerfile layered on top of an existing SGLang ROCm image. It:

• rebuilds ROCr (libhsa-runtime64) + CLR/HIP (libamdhip64) from the exact rocm-systems commit the base image was built from, with the [DO NOT MERGE] test deepgemm warmup error #11212 series cherry-picked on top (so ROCr stays at its native version and remains ABI-compatible with the image's rocminfo/aiter arch detection);
• builds CLR with ROCM_KPACK_ENABLED=ON so the rebuilt libamdhip64 stays compatible with the image's kpack device-code archives;
• swaps the two rebuilt libraries into every ROCm-SDK lib dir in the image and sets ROCPROFILER_QUEUE_INTERPOSITION=0.

Notes

• Default builds are unchanged. This is a separate Dockerfile users build only if they hit the GPU_MAX_HW_QUEUES > 4 decode regression.
• Runtime revert without a rebuild: DEBUG_CLR_DISABLE_ORDERING_EDGE=1.
• Build ARGs (BASE_IMAGE, ROCM_RUNTIME_COMMIT) must be retargeted together for a base image other than the validated default; a mismatched commit risks an ABI break. See docker/rocm-ordering-edge.md.

Test plan

Build-recipe / infra change (no model-code or runtime-default change); no accuracy or perf test applies. Verified the image builds and rocminfo/kernel launch work after the library swap.

Made with Cursor

---

CI States

Latest PR Test (Base): ✅ Run #34745216401
Latest PR Test (Extra): ❌ Run #34745216238
Latest PR Test (AMD ROCm 10): ➖ No AMD PR run found for this commit.

[karverma-amd]

Related: #39314 (Enable DSv4 multi-stream compressor overlap on HIP) depends on this ordering-edge runtime — without the device-resident ordering edges, the multi-stream overlap's cross-stream/multi-queue dispatch cost dominates and the concurrent kernels contend. With this runtime the overlap is clean (−4.5 to −8.5% TPOT at conc 1‑8 on MI355X DeepSeek-V4).