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[XPU] Use SYCL kernels for DeepSeek V4 MHC on XPU - #32166
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Signed-off-by: Cui, Lily <lily.cui@intel.com>
Signed-off-by: Cui, Lily <lily.cui@intel.com>
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Signed-off-by: Cui, Lily <lily.cui@intel.com>
Signed-off-by: Cui, Lily <lily.cui@intel.com>
Signed-off-by: Cui, Lily <lily.cui@intel.com>
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polisettyvarma
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@cyxlily please add intel and xpu labels also if you have permission |
Signed-off-by: Cui, Lily <lily.cui@intel.com>
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Don’t try/except + fall back to TileLang mhc_pre in python/sglang/kernels/ops/layernorm/mhc.py. That file is CUDA/TileLang-only.
Keep XPU dispatch in deepseek_v4.py: lazy-import from sgl_kernel inside _get_mhc_ops() / if _is_xpu: (same as hc_pre today) and fail if the op is missing.
Leave _prewarm_mhc_kernels returning early on XPU — no XPU prewarm in mhc.py.
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Signed-off-by: Cui, Lily <lily.cui@intel.com>
Signed-off-by: Cui, Lily <lily.cui@intel.com>
Signed-off-by: Cui, Lily <lily.cui@intel.com>
Signed-off-by: Cui, Lily <lily.cui@intel.com>
mingfeima
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LGTM. some minors to fix.
Signed-off-by: Cui, Lily <lily.cui@intel.com>
Signed-off-by: Cui, Lily <lily.cui@intel.com>
Signed-off-by: Cui, Lily <lily.cui@intel.com>
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Motivation
Enable XPU-specific optimized kernels for the DeepSeek V4 MHC (Multi-Head Compression) path on Intel XPU hardware. The existing CUDA-path kernels (deep_gemm, CUDA-first device selection) are either unavailable or suboptimal on XPU, causing incorrect device dispatch or missing performance opportunities.
Modifications
deepseek_v4.py: On XPU, dispatch hc_head to sgl_kernel.mhc.fused_hc_head (SYCL kernel) instead of the Triton implementation; dispatch mhc_fused_post_pre to the XPU-specific kernel; fix device selection to avoid falling back to CUDA when XPU is available.
Accuracy Tests
Verified the accuracy of MHC kernels in sgl-kernel-xpu:
hc_head:
sgl-project/sgl-kernel-xpu#345
mhc_fused_post_pre:
sgl-project/sgl-kernel-xpu#302
All configurations pass accuracy tests.
Speed Tests and Profiling
Benchmarked fused_hc_head SYCL kernel vs Triton on Intel XPU (BMG), hc_mult=4, dtype=bfloat16 (median latency, 50 iterations):
Speedup (triton / sycl)
CI States
Latest PR Test (Base): ❌ Run #32685541373
Latest PR Test (Extra): ❌ Run #32685541183
Latest PR Test (AMD ROCm 7.2): ❌ Run #32685541334