[DSv4] Integrate TRT-LLM DSv4 Attention for SM100/103 - #30805
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@akhilg-nv could you fix the conflicts? |
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Adds a uniform FP8 (e4m3, 448 nope + 64 rope = 512 bytes) KV pool.
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@akhilg-nv Please fix the lint and fix conflicts |
b8zhong
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Can we have some more benchmarks in TP {2, 4, 8} with DSV4 head dims?
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/rerun-test test/registered/models_e2e/test_deepseek_v4_flash_fp4_b200_trtllm.py |
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Results for 🚀 |
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/rerun-test test/registered/backends/test_dsv4_fp8_trtllm_backend.py |
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/rerun-test test/registered/models_e2e/test_deepseek_v4_flash_fp4_b200_trtllm.py |
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Results for 🚀 |
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Results for 🚀 |
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| def test_trtllm_semaphore_capacity_covers_configured_query_rows(self): |
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I think this test is a bit overkill. The semaphore issue is a known WAR that TRT-LLM also uses, and I've raised the issue with flashinfer for them to allocate a dedicated, appropriately sized workspace for it. We should pull in that change when it's made, but for now the monkeypatch approach is fine I'm not sure it warrants its own test.
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Sure, can trim it in the next pr or we can deal with this if we need to address other comments together
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All NV pipelines have passed. |
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Do we need #36652 @YAMY1234 @akhilg-nv ? |
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Seperately: flashinfer-ai/flashinfer#4918 might be easier than #32975 |
It is based off of this branch, we will need it as a follow-up to showcase the performance improvements once this is merged. |
I will close #32975 since I have pulled those changes into #36652, and I will investigate the flashinfer change to see if we can use that instead. |
* origin/main: (27 commits) [Simulator] Give the OFFLINE/BLOCKING comparison tolerances real headroom (sgl-project#38732) [Config] msgspec.Struct for the config tier (sgl-project#38753) [AMD] ci: move the miles nightlies from rocm700 to rocm10 (sgl-project#37495) [Config] One writer for the declaration stash; no exception to the write seal (sgl-project#38752) docker(xpu): drop redundant setvars.sh from torch_memory_saver RUN (sgl-project#38665) [XPU][Fix] Pack device-pointer tables as uint64 to avoid 64-bit address overflow (sgl-project#35051) [CI] Temporarily disable GB300 tests (sgl-project#38770) [diffusion] feat: spill large tensors over shared memory like numpy arrays (sgl-project#38656) [diffusion] refactor: refactor utility ownership and document helper placement (sgl-project#38699) [NPU]Support GLM5.2 and FP8 DSA&Indexer kvcache for 950 (sgl-project#38250) [CI] Answer unrecognized slash commands instead of skipping silently (sgl-project#38736) [AMD] Parallelize aiter spec-decode KV index building over token blocks (sgl-project#37659) [DSv4] Integrate TRT-LLM DSv4 Attention for SM100/103 (sgl-project#30805) Add Opt-In for GLM-5.3 Flash breakable prefill CUDA graphs (sgl-project#38522) [CI] Install helion 1.4.0 for the KDA Helion kernel tests (sgl-project#38688) [Rust] Gate health on startup warmup completion (sgl-project#37994) [HiCache] Replace skip_lock_node_ids with a segment lock protocol (sgl-project#36848) feat: add optimized Domino rollout to DFlash V2 (sgl-project#36899) [CI] Add /run-full-ci and /run-extra-ci slash commands (sgl-project#38734) [Model] Support GLM-5.3 Flash NVFP4 loading (sgl-project#38621) ...
Motivation
Integrates TRT-LLM attention kernel for DSv4 style attention (CSA, HCA).
Modifications
Accuracy Tests
GSM8K Accuracy
GSM8K V4-Pro flashmla: 0.965
GSM8K V4-Pro trtllm_gen: 0.985
GPQA
(add --chat-template to above server command)
FlashMLA: Repeat: 8, mean: 0.885
Scores: ['0.889', '0.879', '0.889', '0.879', '0.869', '0.899', '0.904', '0.874']
TRTLLM: Repeat: 8, mean: 0.907
Scores: ['0.919', '0.904', '0.894', '0.904', '0.909', '0.919', '0.904', '0.904']
Speed Tests and Profiling
Unit Kernel Benchmarking (ran with private benchmarking repo):
Prefill: ~1.2x faster
Decode: ~1.45x faster
The performance for TP > 1 scales better on trtllm-gen, since it seems the flashmla variant requires padding the head_dim to 64 or 128. I've attached some sample graphs showing the kernel perf comparison.
E2E bench-serving
flashmla:
trtllm_gen:
Checklist
Review and Merge Process
/tag-and-rerun-ci,/tag-run-ci-label,/rerun-failed-ciCI States
Latest PR Test (Base): ✅ Run #34310903207
Latest PR Test (Extra): ✅ Run #34310902955
Latest PR Test (AMD ROCm 7.2): ❌ Run #34310903174